150 lines
4.9 KiB
Diff
150 lines
4.9 KiB
Diff
From 35f0a707698fc8f20e4164a704d7ac6af3342fb8 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 11 Nov 2011 12:45:24 +0100
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Subject: [PATCH 06/70] MIPS: lantiq: change ltq_request_gpio() call signature
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ltq_request_gpio() was using alt0/1 to multiplex the function of GPIO pins.
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This was XWAY specific. In order to also accomodate SoCs that require more bits
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we use a 32bit mask instead. This way the call signature is consistent between
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XWAY and FALC-ON.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
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---
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 +-
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arch/mips/lantiq/xway/gpio.c | 8 ++--
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arch/mips/lantiq/xway/gpio_stp.c | 6 ++--
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arch/mips/pci/pci-lantiq.c | 36 +++++++++----------
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4 files changed, 26 insertions(+), 28 deletions(-)
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diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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index 9b7ee366..87f6d24 100644
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -135,8 +135,8 @@ extern __iomem void *ltq_ebu_membase;
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extern __iomem void *ltq_cgu_membase;
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/* request a non-gpio and set the PIO config */
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-extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
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- unsigned int alt1, unsigned int dir, const char *name);
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+extern int ltq_gpio_request(unsigned int pin, unsigned int mux,
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+ unsigned int dir, const char *name);
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extern void ltq_pmu_enable(unsigned int module);
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extern void ltq_pmu_disable(unsigned int module);
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extern void ltq_cgu_enable(unsigned int clk);
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diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
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index d2fa98f..f204f6c 100644
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--- a/arch/mips/lantiq/xway/gpio.c
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+++ b/arch/mips/lantiq/xway/gpio.c
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@@ -48,8 +48,8 @@ int irq_to_gpio(unsigned int gpio)
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}
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EXPORT_SYMBOL(irq_to_gpio);
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-int ltq_gpio_request(unsigned int pin, unsigned int alt0,
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- unsigned int alt1, unsigned int dir, const char *name)
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+int ltq_gpio_request(unsigned int pin, unsigned int mux,
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+ unsigned int dir, const char *name)
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{
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int id = 0;
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@@ -67,13 +67,13 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0,
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pin -= PINS_PER_PORT;
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id++;
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}
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- if (alt0)
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+ if (mux & 0x2)
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ltq_gpio_setbit(ltq_gpio_port[id].membase,
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LTQ_GPIO_ALTSEL0, pin);
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else
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ltq_gpio_clearbit(ltq_gpio_port[id].membase,
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LTQ_GPIO_ALTSEL0, pin);
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- if (alt1)
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+ if (mux & 0x1)
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ltq_gpio_setbit(ltq_gpio_port[id].membase,
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LTQ_GPIO_ALTSEL1, pin);
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else
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diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
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index ff9991c..2c78660 100644
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--- a/arch/mips/lantiq/xway/gpio_stp.c
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+++ b/arch/mips/lantiq/xway/gpio_stp.c
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@@ -79,9 +79,9 @@ static struct gpio_chip ltq_stp_chip = {
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static int ltq_stp_hw_init(void)
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{
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/* the 3 pins used to control the external stp */
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- ltq_gpio_request(4, 1, 0, 1, "stp-st");
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- ltq_gpio_request(5, 1, 0, 1, "stp-d");
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- ltq_gpio_request(6, 1, 0, 1, "stp-sh");
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+ ltq_gpio_request(4, 2, 1, "stp-st");
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+ ltq_gpio_request(5, 2, 1, "stp-d");
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+ ltq_gpio_request(6, 2, 1, "stp-sh");
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/* sane defaults */
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ltq_stp_w32(0, LTQ_STP_AR);
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diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
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index be1e1af..c001c5a 100644
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--- a/arch/mips/pci/pci-lantiq.c
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+++ b/arch/mips/pci/pci-lantiq.c
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@@ -70,28 +70,27 @@
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struct ltq_pci_gpio_map {
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int pin;
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- int alt0;
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- int alt1;
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+ int mux;
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int dir;
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char *name;
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};
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/* the pci core can make use of the following gpios */
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static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
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- { 0, 1, 0, 0, "pci-exin0" },
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- { 1, 1, 0, 0, "pci-exin1" },
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- { 2, 1, 0, 0, "pci-exin2" },
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- { 39, 1, 0, 0, "pci-exin3" },
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- { 10, 1, 0, 0, "pci-exin4" },
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- { 9, 1, 0, 0, "pci-exin5" },
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- { 30, 1, 0, 1, "pci-gnt1" },
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- { 23, 1, 0, 1, "pci-gnt2" },
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- { 19, 1, 0, 1, "pci-gnt3" },
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- { 38, 1, 0, 1, "pci-gnt4" },
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- { 29, 1, 0, 0, "pci-req1" },
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- { 31, 1, 0, 0, "pci-req2" },
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- { 3, 1, 0, 0, "pci-req3" },
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- { 37, 1, 0, 0, "pci-req4" },
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+ { 0, 2, 0, "pci-exin0" },
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+ { 1, 2, 0, "pci-exin1" },
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+ { 2, 2, 0, "pci-exin2" },
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+ { 39, 2, 0, "pci-exin3" },
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+ { 10, 2, 0, "pci-exin4" },
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+ { 9, 2, 0, "pci-exin5" },
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+ { 30, 2, 1, "pci-gnt1" },
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+ { 23, 2, 1, "pci-gnt2" },
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+ { 19, 2, 1, "pci-gnt3" },
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+ { 38, 2, 1, "pci-gnt4" },
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+ { 29, 2, 0, "pci-req1" },
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+ { 31, 2, 0, "pci-req2" },
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+ { 3, 2, 0, "pci-req3" },
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+ { 37, 2, 0, "pci-req4" },
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};
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__iomem void *ltq_pci_mapped_cfg;
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@@ -157,13 +156,12 @@ static void ltq_pci_setup_gpio(int gpio)
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for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
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if (gpio & (1 << i)) {
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ltq_gpio_request(ltq_pci_gpio_map[i].pin,
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- ltq_pci_gpio_map[i].alt0,
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- ltq_pci_gpio_map[i].alt1,
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+ ltq_pci_gpio_map[i].mux,
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ltq_pci_gpio_map[i].dir,
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ltq_pci_gpio_map[i].name);
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}
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}
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- ltq_gpio_request(21, 0, 0, 1, "pci-reset");
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+ ltq_gpio_request(21, 0, 1, "pci-reset");
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ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
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}
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--
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1.7.7.1
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