92b3efec54
Sort patches according to target/linux/generic/PATCHES. Additionally: - replace hashes in backported patches with the ones from main Linux tree - add descriptions to some patches Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> [remove 004-add_sata_disk_activity_trigger.patch separately] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
94 lines
3.4 KiB
Diff
94 lines
3.4 KiB
Diff
From 715878016984b2617f6c1f177c50039e12e7bd5b Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
|
|
Date: Thu, 30 Apr 2020 10:06:23 +0200
|
|
Subject: [PATCH] arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio
|
|
function
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
We found out that we are unable to control the PERST# signal via the
|
|
default pin dedicated to be PERST# pin (GPIO2[3] pin) on A3700 SOC when
|
|
this pin is in EP_PCIE1_Resetn mode. There is a register in the PCIe
|
|
register space called PERSTN_GPIO_EN (D0088004[3]), but changing the
|
|
value of this register does not change the pin output when measuring
|
|
with voltmeter.
|
|
|
|
We do not know if this is a bug in the SOC, or if it works only when
|
|
PCIe controller is in a certain state.
|
|
|
|
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready
|
|
before training link") says that when this pin changes pinctrl mode
|
|
from EP_PCIE1_Resetn to GPIO, the PERST# signal is asserted for a brief
|
|
moment.
|
|
|
|
So currently the situation is that on A3700 boards the PERST# signal is
|
|
asserted in U-Boot (because the code in U-Boot issues reset via this pin
|
|
via GPIO mode), and then in Linux by the obscure and undocumented
|
|
mechanism described by the above mentioned commit.
|
|
|
|
We want to issue PERST# signal in a known way, therefore this patch
|
|
changes the pcie_reset_pin function from "pcie" to "gpio" and adds the
|
|
reset-gpios property to the PCIe node in device tree files of
|
|
EspressoBin and Armada 3720 Dev Board (Turris Mox device tree already
|
|
has this property and uDPU does not have a PCIe port).
|
|
|
|
Signed-off-by: Marek Behún <marek.behun@nic.cz>
|
|
Cc: Remi Pommarel <repk@triplefau.lt>
|
|
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
|
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
---
|
|
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 3 +++
|
|
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 1 +
|
|
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 4 ----
|
|
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +-
|
|
4 files changed, 5 insertions(+), 5 deletions(-)
|
|
|
|
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
|
|
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
|
|
@@ -128,6 +128,9 @@
|
|
|
|
/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
|
|
&pcie0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
|
|
+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
@@ -59,6 +59,7 @@
|
|
phys = <&comphy1 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
|
|
+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
/* J6 */
|
|
--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
|
|
+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
|
|
@@ -120,10 +120,6 @@
|
|
};
|
|
};
|
|
|
|
-&pcie_reset_pins {
|
|
- function = "gpio";
|
|
-};
|
|
-
|
|
&pcie0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
|
|
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
@@ -317,7 +317,7 @@
|
|
|
|
pcie_reset_pins: pcie-reset-pins {
|
|
groups = "pcie1";
|
|
- function = "pcie";
|
|
+ function = "gpio";
|
|
};
|
|
|
|
pcie_clkreq_pins: pcie-clkreq-pins {
|