367 lines
10 KiB
Diff
367 lines
10 KiB
Diff
From 878887d15bdee87366b7d3952d1c74c4b68a0782 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 21 Mar 2013 17:49:02 +0100
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Subject: [PATCH 113/164] MIPS: ralink: adds support for MT7620 SoC family
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Add support code for mt7620 SOC.
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The code detects the SoC and registers the clk / pinmux settings.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5177/
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---
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arch/mips/include/asm/mach-ralink/mt7620.h | 76 ++++++++++
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arch/mips/ralink/Kconfig | 3 +
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arch/mips/ralink/Makefile | 1 +
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arch/mips/ralink/Platform | 5 +
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arch/mips/ralink/mt7620.c | 214 ++++++++++++++++++++++++++++
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5 files changed, 299 insertions(+)
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create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
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create mode 100644 arch/mips/ralink/mt7620.c
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diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
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new file mode 100644
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index 0000000..b272649
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -0,0 +1,76 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Parts of this file are based on Ralink's 2.6.21 BSP
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+ *
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+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#ifndef _MT7620_REGS_H_
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+#define _MT7620_REGS_H_
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+
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+#define MT7620_SYSC_BASE 0x10000000
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+
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+#define SYSC_REG_CHIP_NAME0 0x00
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+#define SYSC_REG_CHIP_NAME1 0x04
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+#define SYSC_REG_CHIP_REV 0x0c
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+#define SYSC_REG_SYSTEM_CONFIG0 0x10
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+#define SYSC_REG_SYSTEM_CONFIG1 0x14
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+#define SYSC_REG_CPLL_CONFIG0 0x54
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+#define SYSC_REG_CPLL_CONFIG1 0x58
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+
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+#define MT7620N_CHIP_NAME0 0x33365452
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+#define MT7620N_CHIP_NAME1 0x20203235
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+
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+#define MT7620A_CHIP_NAME0 0x3637544d
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+#define MT7620A_CHIP_NAME1 0x20203032
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+
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+#define CHIP_REV_PKG_MASK 0x1
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+#define CHIP_REV_PKG_SHIFT 16
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+#define CHIP_REV_VER_MASK 0xf
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+#define CHIP_REV_VER_SHIFT 8
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+#define CHIP_REV_ECO_MASK 0xf
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+
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+#define CPLL_SW_CONFIG_SHIFT 31
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+#define CPLL_SW_CONFIG_MASK 0x1
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+#define CPLL_CPU_CLK_SHIFT 24
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+#define CPLL_CPU_CLK_MASK 0x1
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+#define CPLL_MULT_RATIO_SHIFT 16
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+#define CPLL_MULT_RATIO 0x7
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+#define CPLL_DIV_RATIO_SHIFT 10
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+#define CPLL_DIV_RATIO 0x3
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+
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+#define SYSCFG0_DRAM_TYPE_MASK 0x3
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+#define SYSCFG0_DRAM_TYPE_SHIFT 4
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+#define SYSCFG0_DRAM_TYPE_SDRAM 0
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+#define SYSCFG0_DRAM_TYPE_DDR1 1
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+#define SYSCFG0_DRAM_TYPE_DDR2 2
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+
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+#define MT7620_GPIO_MODE_I2C BIT(0)
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+#define MT7620_GPIO_MODE_UART0_SHIFT 2
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+#define MT7620_GPIO_MODE_UART0_MASK 0x7
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+#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
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+#define MT7620_GPIO_MODE_UARTF 0x0
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+#define MT7620_GPIO_MODE_PCM_UARTF 0x1
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+#define MT7620_GPIO_MODE_PCM_I2S 0x2
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+#define MT7620_GPIO_MODE_I2S_UARTF 0x3
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+#define MT7620_GPIO_MODE_PCM_GPIO 0x4
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+#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
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+#define MT7620_GPIO_MODE_GPIO_I2S 0x6
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+#define MT7620_GPIO_MODE_GPIO 0x7
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+#define MT7620_GPIO_MODE_UART1 BIT(5)
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+#define MT7620_GPIO_MODE_MDIO BIT(8)
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+#define MT7620_GPIO_MODE_RGMII1 BIT(9)
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+#define MT7620_GPIO_MODE_RGMII2 BIT(10)
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+#define MT7620_GPIO_MODE_SPI BIT(11)
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+#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
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+#define MT7620_GPIO_MODE_WLED BIT(13)
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+#define MT7620_GPIO_MODE_JTAG BIT(15)
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+#define MT7620_GPIO_MODE_EPHY BIT(15)
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+#define MT7620_GPIO_MODE_WDT BIT(22)
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+
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+#endif
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diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
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index ce57d3e..86f6c77 100644
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--- a/arch/mips/ralink/Kconfig
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+++ b/arch/mips/ralink/Kconfig
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@@ -20,6 +20,9 @@ choice
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select USB_ARCH_HAS_OHCI
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select USB_ARCH_HAS_EHCI
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+ config SOC_MT7620
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+ bool "MT7620"
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+
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endchoice
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choice
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diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
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index ba9669c..38cf1a8 100644
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--- a/arch/mips/ralink/Makefile
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+++ b/arch/mips/ralink/Makefile
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@@ -11,6 +11,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
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obj-$(CONFIG_SOC_RT288X) += rt288x.o
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obj-$(CONFIG_SOC_RT305X) += rt305x.o
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obj-$(CONFIG_SOC_RT3883) += rt3883.o
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+obj-$(CONFIG_SOC_MT7620) += mt7620.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
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index f67c08d..b2cbf16 100644
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--- a/arch/mips/ralink/Platform
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+++ b/arch/mips/ralink/Platform
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@@ -18,3 +18,8 @@ load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
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# Ralink RT3883
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#
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load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
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+
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+#
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+# Ralink MT7620
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+#
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+load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
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diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
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new file mode 100644
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index 0000000..eb00ab8
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--- /dev/null
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+++ b/arch/mips/ralink/mt7620.c
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@@ -0,0 +1,214 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Parts of this file are based on Ralink's 2.6.21 BSP
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+ *
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+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/module.h>
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+
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+#include <asm/mipsregs.h>
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+#include <asm/mach-ralink/ralink_regs.h>
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+#include <asm/mach-ralink/mt7620.h>
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+
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+#include "common.h"
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+
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+/* does the board have sdram or ddram */
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+static int dram_type;
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+
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+/* the pll dividers */
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+static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
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+
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+static struct ralink_pinmux_grp mode_mux[] = {
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+ {
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+ .name = "i2c",
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+ .mask = MT7620_GPIO_MODE_I2C,
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+ .gpio_first = 1,
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+ .gpio_last = 2,
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+ }, {
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+ .name = "spi",
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+ .mask = MT7620_GPIO_MODE_SPI,
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+ .gpio_first = 3,
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+ .gpio_last = 6,
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+ }, {
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+ .name = "uartlite",
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+ .mask = MT7620_GPIO_MODE_UART1,
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+ .gpio_first = 15,
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+ .gpio_last = 16,
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+ }, {
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+ .name = "wdt",
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+ .mask = MT7620_GPIO_MODE_WDT,
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+ .gpio_first = 17,
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+ .gpio_last = 17,
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+ }, {
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+ .name = "mdio",
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+ .mask = MT7620_GPIO_MODE_MDIO,
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+ .gpio_first = 22,
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+ .gpio_last = 23,
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+ }, {
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+ .name = "rgmii1",
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+ .mask = MT7620_GPIO_MODE_RGMII1,
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+ .gpio_first = 24,
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+ .gpio_last = 35,
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+ }, {
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+ .name = "spi refclk",
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+ .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
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+ .gpio_first = 37,
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+ .gpio_last = 39,
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+ }, {
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+ .name = "jtag",
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+ .mask = MT7620_GPIO_MODE_JTAG,
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+ .gpio_first = 40,
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+ .gpio_last = 44,
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+ }, {
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+ /* shared lines with jtag */
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+ .name = "ephy",
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+ .mask = MT7620_GPIO_MODE_EPHY,
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+ .gpio_first = 40,
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+ .gpio_last = 44,
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+ }, {
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+ .name = "nand",
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+ .mask = MT7620_GPIO_MODE_JTAG,
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+ .gpio_first = 45,
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+ .gpio_last = 59,
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+ }, {
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+ .name = "rgmii2",
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+ .mask = MT7620_GPIO_MODE_RGMII2,
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+ .gpio_first = 60,
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+ .gpio_last = 71,
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+ }, {
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+ .name = "wled",
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+ .mask = MT7620_GPIO_MODE_WLED,
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+ .gpio_first = 72,
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+ .gpio_last = 72,
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+ }, {0}
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+};
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+
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+static struct ralink_pinmux_grp uart_mux[] = {
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+ {
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+ .name = "uartf",
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+ .mask = MT7620_GPIO_MODE_UARTF,
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+ .gpio_first = 7,
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+ .gpio_last = 14,
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+ }, {
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+ .name = "pcm uartf",
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+ .mask = MT7620_GPIO_MODE_PCM_UARTF,
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+ .gpio_first = 7,
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+ .gpio_last = 14,
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+ }, {
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+ .name = "pcm i2s",
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+ .mask = MT7620_GPIO_MODE_PCM_I2S,
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+ .gpio_first = 7,
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+ .gpio_last = 14,
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+ }, {
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+ .name = "i2s uartf",
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+ .mask = MT7620_GPIO_MODE_I2S_UARTF,
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+ .gpio_first = 7,
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+ .gpio_last = 14,
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+ }, {
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+ .name = "pcm gpio",
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+ .mask = MT7620_GPIO_MODE_PCM_GPIO,
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+ .gpio_first = 11,
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+ .gpio_last = 14,
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+ }, {
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+ .name = "gpio uartf",
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+ .mask = MT7620_GPIO_MODE_GPIO_UARTF,
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+ .gpio_first = 7,
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+ .gpio_last = 10,
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+ }, {
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+ .name = "gpio i2s",
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+ .mask = MT7620_GPIO_MODE_GPIO_I2S,
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+ .gpio_first = 7,
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+ .gpio_last = 10,
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+ }, {
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+ .name = "gpio",
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+ .mask = MT7620_GPIO_MODE_GPIO,
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+ }, {0}
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+};
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+
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+struct ralink_pinmux rt_gpio_pinmux = {
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+ .mode = mode_mux,
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+ .uart = uart_mux,
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+ .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
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+ .uart_mask = MT7620_GPIO_MODE_GPIO,
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+};
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+
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+void __init ralink_clk_init(void)
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+{
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+ unsigned long cpu_rate, sys_rate;
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+ u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
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+ u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
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+ u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
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+ u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
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+
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+ if (cpu_clk) {
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+ cpu_rate = 480000000;
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+ } else if (!swconfig) {
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+ cpu_rate = 600000000;
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+ } else {
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+ u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
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+ u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
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+
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+ cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
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+ }
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+
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+ if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
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+ sys_rate = cpu_rate / 4;
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+ else
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+ sys_rate = cpu_rate / 3;
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+
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+ ralink_clk_add("cpu", cpu_rate);
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+ ralink_clk_add("10000100.timer", 40000000);
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+ ralink_clk_add("10000500.uart", 40000000);
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+ ralink_clk_add("10000c00.uartlite", 40000000);
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+}
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+
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+void __init ralink_of_remap(void)
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+{
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+ rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
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+ rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
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+
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+ if (!rt_sysc_membase || !rt_memc_membase)
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+ panic("Failed to remap core resources");
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+}
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+
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+void prom_soc_init(struct ralink_soc_info *soc_info)
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+{
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+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
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+ unsigned char *name = NULL;
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+ u32 n0;
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+ u32 n1;
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+ u32 rev;
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+ u32 cfg0;
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+
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+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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+
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+ if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
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+ name = "MT7620N";
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+ soc_info->compatible = "ralink,mt7620n-soc";
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+ } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
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+ name = "MT7620A";
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+ soc_info->compatible = "ralink,mt7620a-soc";
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+ } else {
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+ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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+ }
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+
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+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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+
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+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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+ "Ralink %s ver:%u eco:%u",
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+ name,
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+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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+ (rev & CHIP_REV_ECO_MASK));
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+
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+ cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
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+ dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
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+}
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--
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1.7.10.4
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