3af779eb17
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.11, and Linux v3.12. This work mainly covers: * Ground work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family,and the Armada family. * Further updates to the mvebu MBus. * Work and ground work for enabling MSI on the Armada family. * some phy / mdio bus initialization related work. * Device tree binding documentation update. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39565
110 lines
3.5 KiB
Diff
110 lines
3.5 KiB
Diff
From be448338edda73460dc3e8c005b17edddf1c1b4f Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 6 Jun 2013 18:27:16 +0200
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Subject: [PATCH 078/203] PCI: mvebu: add support for MSI
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This commit adds support for Message Signaled Interrupts in the
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Marvell PCIe host controller. The work is very simple: it simply gets
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a reference to the msi_chip associated to the PCIe controller thanks
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to the msi-parent DT property, and stores this reference in the
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pci_bus structure. This is enough to let the Linux PCI core use the
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functions of msi_chip to setup and teardown MSIs.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
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Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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---
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.../devicetree/bindings/pci/mvebu-pci.txt | 3 +++
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drivers/pci/host/pci-mvebu.c | 26 ++++++++++++++++++++++
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2 files changed, 29 insertions(+)
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--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
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+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
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@@ -14,6 +14,8 @@ Mandatory properties:
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interfaces, and ranges describing the MBus windows needed to access
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the memory and I/O regions of each PCIe interface.
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+- msi-parent: Link to the hardware entity that serves as the Message
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+ Signaled Interrupt controller for this PCI controller.
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The ranges describing the MMIO registers have the following layout:
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0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
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@@ -85,6 +87,7 @@ pcie-controller {
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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+ msi-parent = <&mpic>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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--- a/drivers/pci/host/pci-mvebu.c
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+++ b/drivers/pci/host/pci-mvebu.c
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@@ -11,6 +11,7 @@
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/mbus.h>
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+#include <linux/msi.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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@@ -103,6 +104,7 @@ struct mvebu_pcie_port;
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struct mvebu_pcie {
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struct platform_device *pdev;
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struct mvebu_pcie_port *ports;
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+ struct msi_chip *msi;
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struct resource io;
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struct resource realio;
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struct resource mem;
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@@ -673,6 +675,12 @@ static struct pci_bus *mvebu_pcie_scan_b
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return bus;
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}
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+void mvebu_pcie_add_bus(struct pci_bus *bus)
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+{
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+ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
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+ bus->msi = pcie->msi;
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+}
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+
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resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
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const struct resource *res,
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resource_size_t start,
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@@ -709,6 +717,7 @@ static void __init mvebu_pcie_enable(str
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hw.map_irq = mvebu_pcie_map_irq;
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hw.ops = &mvebu_pcie_ops;
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hw.align_resource = mvebu_pcie_align_resource;
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+ hw.add_bus = mvebu_pcie_add_bus;
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pci_common_init(&hw);
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}
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@@ -733,6 +742,21 @@ mvebu_pcie_map_registers(struct platform
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return devm_request_and_ioremap(&pdev->dev, ®s);
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}
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+static void __init mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
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+{
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+ struct device_node *msi_node;
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+
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+ msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
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+ "msi-parent", 0);
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+ if (!msi_node)
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+ return;
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+
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+ pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
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+
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+ if (pcie->msi)
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+ pcie->msi->dev = &pcie->pdev->dev;
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+}
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+
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#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
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#define DT_TYPE_IO 0x1
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#define DT_TYPE_MEM32 0x2
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@@ -911,6 +935,8 @@ static int __init mvebu_pcie_probe(struc
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i++;
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}
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+ mvebu_pcie_msi_enable(pcie);
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+
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mvebu_pcie_enable(pcie);
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return 0;
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