69d323f231
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.10, and Linux v3.11. This work mainly covers: * Enabling USB storage, and PCI to mvebu_defconfig. * Add support for NOR flash. * Some PCI device tree related updates, and bus parsing. * Adding Armada XP & 370 PCI driver, and update some clock gating specifics. * Introduce Marvell EBU Device Bus driver. * Enaling USB in the armada*.dts. * Enabling, and updating the mvebu-mbus. * Some SATA and Ethernet related fixes. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39564
92 lines
2.7 KiB
Diff
92 lines
2.7 KiB
Diff
From 88260610ea7a2c5a164721af28f59856880221b4 Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 6 Jun 2013 12:24:28 +0200
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Subject: [PATCH 028/203] arm: mvebu: don't hardcode a physical address in
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headsmp.S
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Now that the coherency_init() function is called a bit earlier, we can
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actually read the physical address of the coherency unit registers
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from the Device Tree, and communicate that to the headsmp.S code,
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which avoids hardcoding a physical address.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Acked-by: Arnd Bergmann <arnd@arndb.de>
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Reviewed-by: Will Deacon <will.deacon@arm.com>
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Acked-by: Nicolas Pitre <nico@linaro.org>
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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---
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arch/arm/mach-mvebu/coherency.c | 12 ++++++++++++
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arch/arm/mach-mvebu/headsmp.S | 16 ++++++++--------
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2 files changed, 20 insertions(+), 8 deletions(-)
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--- a/arch/arm/mach-mvebu/coherency.c
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+++ b/arch/arm/mach-mvebu/coherency.c
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@@ -25,8 +25,10 @@
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <asm/smp_plat.h>
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+#include <asm/cacheflush.h>
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#include "armada-370-xp.h"
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+unsigned long __cpuinitdata coherency_phys_base;
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static void __iomem *coherency_base;
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static void __iomem *coherency_cpu_base;
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@@ -124,7 +126,17 @@ int __init coherency_init(void)
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np = of_find_matching_node(NULL, of_coherency_table);
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if (np) {
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+ struct resource res;
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pr_info("Initializing Coherency fabric\n");
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+ of_address_to_resource(np, 0, &res);
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+ coherency_phys_base = res.start;
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+ /*
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+ * Ensure secondary CPUs will see the updated value,
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+ * which they read before they join the coherency
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+ * fabric, and therefore before they are coherent with
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+ * the boot CPU cache.
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+ */
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+ sync_cache_w(&coherency_phys_base);
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coherency_base = of_iomap(np, 0);
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coherency_cpu_base = of_iomap(np, 1);
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set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
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--- a/arch/arm/mach-mvebu/headsmp.S
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+++ b/arch/arm/mach-mvebu/headsmp.S
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@@ -21,12 +21,6 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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-/*
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- * At this stage the secondary CPUs don't have acces yet to the MMU, so
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- * we have to provide physical addresses
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- */
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-#define ARMADA_XP_CFB_BASE 0xD0020200
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-
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__CPUINIT
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/*
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@@ -35,15 +29,21 @@
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* startup
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*/
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ENTRY(armada_xp_secondary_startup)
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+ /* Get coherency fabric base physical address */
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+ adr r0, 1f
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+ ldr r1, [r0]
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+ ldr r0, [r0, r1]
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/* Read CPU id */
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mrc p15, 0, r1, c0, c0, 5
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and r1, r1, #0xF
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/* Add CPU to coherency fabric */
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- ldr r0, =ARMADA_XP_CFB_BASE
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-
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bl ll_set_cpu_coherent
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b secondary_startup
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ENDPROC(armada_xp_secondary_startup)
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+
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+ .align 2
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+1:
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+ .long coherency_phys_base - .
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