e395433178
Only netboot tested. Flash at your own risk. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 47702
136 lines
4.4 KiB
Diff
136 lines
4.4 KiB
Diff
From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sun, 3 Jul 2011 15:00:38 +0200
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Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/bcm63xx/dev-flash.c | 35 +++++++++++++++++++-
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 +
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2 files changed, 33 insertions(+), 2 deletions(-)
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--- a/arch/mips/bcm63xx/dev-flash.c
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+++ b/arch/mips/bcm63xx/dev-flash.c
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@@ -17,9 +17,12 @@
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/spi-nor.h>
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+#include <linux/spi/spi.h>
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+#include <linux/spi/flash.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_dev_flash.h>
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+#include <bcm63xx_dev_hsspi.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_io.h>
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@@ -66,6 +69,21 @@ void __init bcm63xx_flash_force_phys_bas
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mtd_resources[0].end = end;
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}
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+static struct flash_platform_data bcm63xx_flash_data = {
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+ .part_probe_types = bcm63xx_part_types,
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+};
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+
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+static struct spi_board_info bcm63xx_spi_flash_info[] = {
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+ {
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+ .bus_num = 0,
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+ .chip_select = 0,
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+ .mode = 0,
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+ .max_speed_hz = 781000,
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+ .modalias = "m25p80",
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+ .platform_data = &bcm63xx_flash_data,
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+ },
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+};
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+
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static int __init bcm63xx_detect_flash_type(void)
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{
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u32 val;
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@@ -73,9 +91,15 @@ static int __init bcm63xx_detect_flash_t
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switch (bcm63xx_get_cpu_id()) {
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case BCM6318_CPU_ID:
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/* only support serial flash */
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+ bcm63xx_spi_flash_info[0].max_speed_hz = 62500000;
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return BCM63XX_FLASH_TYPE_SERIAL;
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case BCM6328_CPU_ID:
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val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
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+ if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
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+ bcm63xx_spi_flash_info[0].max_speed_hz = 33333334;
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+ else
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+ bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
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+
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if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
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return BCM63XX_FLASH_TYPE_SERIAL;
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else
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@@ -94,12 +118,20 @@ static int __init bcm63xx_detect_flash_t
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return BCM63XX_FLASH_TYPE_SERIAL;
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case BCM6362_CPU_ID:
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val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
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+ if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
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+ bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
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+ else
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+ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
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+
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if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
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return BCM63XX_FLASH_TYPE_SERIAL;
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else
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return BCM63XX_FLASH_TYPE_NAND;
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case BCM6368_CPU_ID:
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val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
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+ if (val & STRAPBUS_6368_SPI_CLK_FAST)
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+ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
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+
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switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
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case STRAPBUS_6368_BOOT_SEL_NAND:
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return BCM63XX_FLASH_TYPE_NAND;
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@@ -110,6 +142,11 @@ static int __init bcm63xx_detect_flash_t
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}
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case BCM63268_CPU_ID:
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val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
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+ if (val & STRAPBUS_63268_HSSPI_CLK_FAST)
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+ bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
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+ else
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+ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
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+
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if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
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return BCM63XX_FLASH_TYPE_SERIAL;
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else
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@@ -195,8 +232,17 @@ int __init bcm63xx_flash_register(void)
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return platform_device_register(&mtd_dev);
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case BCM63XX_FLASH_TYPE_SERIAL:
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- pr_warn("unsupported serial flash detected\n");
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- return -ENODEV;
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+ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
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+ BCMCPU_IS_63268()) {
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+ bcm63xx_spi_flash_info[0].bus_num = 1;
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+ bcm63xx_spi_flash_info[0].mode = SPI_RX_DUAL;
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+ }
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+
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+ if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
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+ bcm63xx_flash_data.max_transfer_len = SPI_6358_MSG_DATA_SIZE;
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+
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+ return spi_register_board_info(bcm63xx_spi_flash_info,
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+ ARRAY_SIZE(bcm63xx_spi_flash_info));
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case BCM63XX_FLASH_TYPE_NAND:
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pr_warn("unsupported NAND flash detected\n");
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return -ENODEV;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -708,6 +708,7 @@
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#define GPIO_STRAPBUS_REG 0x40
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#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
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#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
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+#define STRAPBUS_6368_SPI_CLK_FAST (1 << 6)
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#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
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#define STRAPBUS_6368_BOOT_SEL_NAND 0
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#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
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@@ -1564,6 +1565,7 @@
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#define IDDQ_CTRL_63268_USBH (1 << 4)
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#define MISC_STRAPBUS_6328_REG 0x240
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+#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4)
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#define STRAPBUS_6328_FCVO_SHIFT 7
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#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
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#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
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