Openwrt/target/linux/ath79/dts/qca9563_rosinson_wr818.dts
Adrian Schmutzler 3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00

150 lines
2.2 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca956x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "ROSINSON WR818";
compatible = "rosinson,wr818", "qca,qca9563";
aliases {
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
};
leds {
compatible = "gpio-leds";
led_system: system {
label = "red:system";
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
wifi_2g {
label = "red:wifi2g";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x040000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x040000 0x010000>;
read-only;
};
info: partition@50000 {
label = "factory";
reg = <0x050000 0x010000>;
read-only;
};
partition@60000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x060000 0xf80000>;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&mdio0 {
status = "okay";
phy-mask = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "sgmii";
qca,ar8327-initvals = <
0x04 0x00080080 /* PORT0 PAD MODE CTRL */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
};
&eth0 {
status = "okay";
mtd-mac-address = <&info 0x0>;
phy-mode = "sgmii";
phy-handle = <&phy0>;
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
};
&usb_phy0 {
status = "okay";
};
&usb0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&usb_phy1 {
status = "okay";
};
&usb1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};