Openwrt/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts
Adrian Schmutzler 3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca955x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "openmesh,om5p-ac-v2", "qca,qca9558";
model = "OpenMesh OM5P-AC V2";
extosc: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "ref";
clock-frequency = <40000000>;
};
leds {
compatible = "gpio-leds";
power {
label = "blue:power";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
};
wifi_green {
label = "green:wifi";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
};
wifi_yellow {
label = "yellow:wifi";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
wifi_red {
label = "red:wifi";
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
};
gpio-export {
compatible = "gpio-export";
#size-cells = <0>;
gpio_pa_dcdc {
gpio-export,name = "om5pac:pa_dcdc";
gpio-export,output = <1>;
gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
};
gpio_pa_high {
gpio-export,name = "om5pac:pa_high";
gpio-export,output = <1>;
gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
};
};
};
&pinmux {
pinmux_pa_dcdc_pins {
pinctrl-single,bits = <0x0 0xff00 0x0>;
};
pinmux_pa_high_pins {
pinctrl-single,bits = <0x10 0xff 0x0>;
};
};
&pcie0 {
status = "okay";
};
&pll {
clocks = <&extosc>;
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x040000>;
read-only;
};
partition@1 {
label = "u-boot-env";
reg = <0x040000 0x010000>;
};
partition@2 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x850000 0x7a0000>;
};
partition@3 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&mdio0 {
status = "okay";
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii-id";
};
};
&mdio1 {
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
phy-mode = "sgmii";
};
};
&eth0 {
status = "okay";
pll-data = <0x82000101 0x80000101 0x80001313>;
phy-handle = <&phy4>;
};
&eth1 {
status = "okay";
pll-data = <0x03000101 0x80000101 0x80001313>;
phy-handle = <&phy1>;
};