529 lines
13 KiB
Diff
529 lines
13 KiB
Diff
From cfb23fbd5be0276507a8af15be0738a7834555b5 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 22 Apr 2013 23:16:18 +0200
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Subject: [PATCH 58/79] SPI: ralink: add Ralink SoC spi driver
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Add the driver needed to make SPI work on Ralink SoC.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/spi/Kconfig | 6 +
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-ralink.c | 475 ++++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 482 insertions(+)
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create mode 100644 drivers/spi/spi-ralink.c
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diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
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index 2e188e1..76c489a 100644
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -315,6 +315,12 @@ config SPI_RSPI
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help
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SPI driver for Renesas RSPI blocks.
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+config SPI_RALINK
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+ tristate "Ralink RT288x/RT305x/RT3662 SPI Controller"
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+ depends on (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620)
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+ help
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+ This selects a driver for the Ralink RT288x/RT305x SPI Controller.
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+
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config SPI_S3C24XX
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tristate "Samsung S3C24XX series SPI"
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depends on ARCH_S3C24XX && EXPERIMENTAL
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diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
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index 64e970b..5b73cf8 100644
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
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obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o
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obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
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obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
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+obj-$(CONFIG_SPI_RALINK) += spi-ralink.o
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obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
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spi-s3c24xx-hw-y := spi-s3c24xx.o
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spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
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diff --git a/drivers/spi/spi-ralink.c b/drivers/spi/spi-ralink.c
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new file mode 100644
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index 0000000..b07cbaa
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--- /dev/null
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+++ b/drivers/spi/spi-ralink.c
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@@ -0,0 +1,475 @@
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+/*
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+ * spi-ralink.c -- Ralink RT288x/RT305x SPI controller driver
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+ *
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+ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
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+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * Some parts are based on spi-orion.c:
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+ * Author: Shadi Ammouri <shadi@marvell.com>
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+ * Copyright (C) 2007-2008 Marvell Ltd.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <linux/reset.h>
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+#include <linux/spi/spi.h>
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+#include <linux/platform_device.h>
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+
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+#define DRIVER_NAME "spi-ralink"
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+#define RALINK_NUM_CHIPSELECTS 1 /* only one slave is supported*/
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+#define RALINK_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
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+
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+#define RAMIPS_SPI_STAT 0x00
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+#define RAMIPS_SPI_CFG 0x10
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+#define RAMIPS_SPI_CTL 0x14
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+#define RAMIPS_SPI_DATA 0x20
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+
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+/* SPISTAT register bit field */
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+#define SPISTAT_BUSY BIT(0)
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+
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+/* SPICFG register bit field */
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+#define SPICFG_LSBFIRST 0
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+#define SPICFG_MSBFIRST BIT(8)
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+#define SPICFG_SPICLKPOL BIT(6)
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+#define SPICFG_RXCLKEDGE_FALLING BIT(5)
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+#define SPICFG_TXCLKEDGE_FALLING BIT(4)
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+#define SPICFG_SPICLK_PRESCALE_MASK 0x7
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+#define SPICFG_SPICLK_DIV2 0
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+#define SPICFG_SPICLK_DIV4 1
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+#define SPICFG_SPICLK_DIV8 2
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+#define SPICFG_SPICLK_DIV16 3
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+#define SPICFG_SPICLK_DIV32 4
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+#define SPICFG_SPICLK_DIV64 5
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+#define SPICFG_SPICLK_DIV128 6
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+#define SPICFG_SPICLK_DISABLE 7
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+
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+/* SPICTL register bit field */
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+#define SPICTL_HIZSDO BIT(3)
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+#define SPICTL_STARTWR BIT(2)
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+#define SPICTL_STARTRD BIT(1)
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+#define SPICTL_SPIENA BIT(0)
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+
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+#ifdef DEBUG
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+#define spi_debug(args...) printk(args)
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+#else
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+#define spi_debug(args...)
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+#endif
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+
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+struct ralink_spi {
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+ struct spi_master *master;
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+ void __iomem *base;
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+ unsigned int sys_freq;
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+ unsigned int speed;
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+ struct clk *clk;
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+};
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+
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+static inline struct ralink_spi *spidev_to_ralink_spi(struct spi_device *spi)
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+{
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+ return spi_master_get_devdata(spi->master);
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+}
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+
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+static inline u32 ralink_spi_read(struct ralink_spi *rs, u32 reg)
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+{
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+ return ioread32(rs->base + reg);
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+}
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+
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+static inline void ralink_spi_write(struct ralink_spi *rs, u32 reg, u32 val)
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+{
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+ iowrite32(val, rs->base + reg);
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+}
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+
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+static inline void ralink_spi_setbits(struct ralink_spi *rs, u32 reg, u32 mask)
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+{
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+ void __iomem *addr = rs->base + reg;
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+ u32 val;
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+
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+ val = ioread32(addr);
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+ val |= mask;
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+ iowrite32(val, addr);
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+}
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+
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+static inline void ralink_spi_clrbits(struct ralink_spi *rs, u32 reg, u32 mask)
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+{
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+ void __iomem *addr = rs->base + reg;
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+ u32 val;
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+
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+ val = ioread32(addr);
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+ val &= ~mask;
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+ iowrite32(val, addr);
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+}
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+
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+static int ralink_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
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+{
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+ struct ralink_spi *rs = spidev_to_ralink_spi(spi);
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+ u32 rate;
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+ u32 prescale;
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+ u32 reg;
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+
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+ spi_debug("%s: speed:%u\n", __func__, speed);
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+
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+ /*
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+ * the supported rates are: 2, 4, 8, ... 128
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+ * round up as we look for equal or less speed
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+ */
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+ rate = DIV_ROUND_UP(rs->sys_freq, speed);
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+ spi_debug("%s: rate-1:%u\n", __func__, rate);
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+ rate = roundup_pow_of_two(rate);
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+ spi_debug("%s: rate-2:%u\n", __func__, rate);
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+
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+ /* check if requested speed is too small */
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+ if (rate > 128)
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+ return -EINVAL;
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+
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+ if (rate < 2)
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+ rate = 2;
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+
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+ /* Convert the rate to SPI clock divisor value. */
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+ prescale = ilog2(rate/2);
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+ spi_debug("%s: prescale:%u\n", __func__, prescale);
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+
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+ reg = ralink_spi_read(rs, RAMIPS_SPI_CFG);
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+ reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
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+ ralink_spi_write(rs, RAMIPS_SPI_CFG, reg);
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+ rs->speed = speed;
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+ return 0;
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+}
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+
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+/*
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+ * called only when no transfer is active on the bus
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+ */
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+static int
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+ralink_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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+{
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+ struct ralink_spi *rs = spidev_to_ralink_spi(spi);
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+ unsigned int speed = spi->max_speed_hz;
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+ int rc;
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+ unsigned int bits_per_word = 8;
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+
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+ if ((t != NULL) && t->speed_hz)
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+ speed = t->speed_hz;
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+
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+ if ((t != NULL) && t->bits_per_word)
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+ bits_per_word = t->bits_per_word;
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+
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+ if (rs->speed != speed) {
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+ spi_debug("%s: speed_hz:%u\n", __func__, speed);
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+ rc = ralink_spi_baudrate_set(spi, speed);
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+ if (rc)
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+ return rc;
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+ }
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+
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+ if (bits_per_word != 8) {
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+ spi_debug("%s: bad bits_per_word: %u\n", __func__,
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+ bits_per_word);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static void ralink_spi_set_cs(struct ralink_spi *rs, int enable)
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+{
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+ if (enable)
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+ ralink_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
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+ else
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+ ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
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+}
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+
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+static inline int ralink_spi_wait_till_ready(struct ralink_spi *rs)
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+{
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+ int i;
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+
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+ for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
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+ u32 status;
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+
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+ status = ralink_spi_read(rs, RAMIPS_SPI_STAT);
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+ if ((status & SPISTAT_BUSY) == 0)
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+ return 0;
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+
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+ udelay(1);
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+ }
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+
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+ return -ETIMEDOUT;
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+}
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+
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+static unsigned int
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+ralink_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
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+{
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+ struct ralink_spi *rs = spidev_to_ralink_spi(spi);
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+ unsigned count = 0;
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+ u8 *rx = xfer->rx_buf;
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+ const u8 *tx = xfer->tx_buf;
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+ int err;
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+
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+ spi_debug("%s(%d): %s %s\n", __func__, xfer->len,
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+ (tx != NULL) ? "tx" : " ",
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+ (rx != NULL) ? "rx" : " ");
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+
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+ if (tx) {
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+ for (count = 0; count < xfer->len; count++) {
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+ ralink_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
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+ ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
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+ err = ralink_spi_wait_till_ready(rs);
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+ if (err) {
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+ dev_err(&spi->dev, "TX failed, err=%d\n", err);
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+ goto out;
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+ }
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+ }
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+ }
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+
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+ if (rx) {
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+ for (count = 0; count < xfer->len; count++) {
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+ ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
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+ err = ralink_spi_wait_till_ready(rs);
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+ if (err) {
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+ dev_err(&spi->dev, "RX failed, err=%d\n", err);
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+ goto out;
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+ }
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+ rx[count] = (u8) ralink_spi_read(rs, RAMIPS_SPI_DATA);
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+ }
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+ }
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+
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+out:
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+ return count;
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+}
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+
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+static int ralink_spi_transfer_one_message(struct spi_master *master,
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+ struct spi_message *m)
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+{
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+ struct ralink_spi *rs = spi_master_get_devdata(master);
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+ struct spi_device *spi = m->spi;
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+ struct spi_transfer *t = NULL;
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+ int par_override = 0;
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+ int status = 0;
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+ int cs_active = 0;
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+
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+ /* Load defaults */
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+ status = ralink_spi_setup_transfer(spi, NULL);
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+ if (status < 0)
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+ goto msg_done;
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+
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ unsigned int bits_per_word = spi->bits_per_word;
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+
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+ if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
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+ dev_err(&spi->dev,
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+ "message rejected: invalid transfer data buffers\n");
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+ status = -EIO;
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+ goto msg_done;
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+ }
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+
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+ if (t->bits_per_word)
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+ bits_per_word = t->bits_per_word;
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+
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+ if (bits_per_word != 8) {
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+ dev_err(&spi->dev,
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+ "message rejected: invalid transfer bits_per_word (%d bits)\n",
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+ bits_per_word);
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+ status = -EIO;
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+ goto msg_done;
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+ }
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+
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+ if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
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+ dev_err(&spi->dev,
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+ "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
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+ (rs->sys_freq / 128), t->speed_hz);
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+ status = -EIO;
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+ goto msg_done;
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+ }
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+
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+ if (par_override || t->speed_hz || t->bits_per_word) {
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+ par_override = 1;
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+ status = ralink_spi_setup_transfer(spi, t);
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+ if (status < 0)
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+ goto msg_done;
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+ if (!t->speed_hz && !t->bits_per_word)
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+ par_override = 0;
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+ }
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+
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+ if (!cs_active) {
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+ ralink_spi_set_cs(rs, 1);
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+ cs_active = 1;
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+ }
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+
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+ if (t->len)
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+ m->actual_length += ralink_spi_write_read(spi, t);
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+
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+ if (t->delay_usecs)
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+ udelay(t->delay_usecs);
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+
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+ if (t->cs_change) {
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+ ralink_spi_set_cs(rs, 0);
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+ cs_active = 0;
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+ }
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+ }
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+
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+msg_done:
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+ if (cs_active)
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+ ralink_spi_set_cs(rs, 0);
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+
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+ m->status = status;
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+ spi_finalize_current_message(master);
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+
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+ return 0;
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+}
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+
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+static int ralink_spi_setup(struct spi_device *spi)
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+{
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+ struct ralink_spi *rs = spidev_to_ralink_spi(spi);
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+
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+ if ((spi->max_speed_hz == 0) ||
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+ (spi->max_speed_hz > (rs->sys_freq / 2)))
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+ spi->max_speed_hz = (rs->sys_freq / 2);
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+
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+ if (spi->max_speed_hz < (rs->sys_freq / 128)) {
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+ dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
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+ spi->max_speed_hz);
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+ return -EINVAL;
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+ }
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+
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+ if (spi->bits_per_word != 0 && spi->bits_per_word != 8) {
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+ dev_err(&spi->dev,
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+ "setup: requested bits per words - os wrong %d bpw\n",
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+ spi->bits_per_word);
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+ return -EINVAL;
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+ }
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+
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+ if (spi->bits_per_word == 0)
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+ spi->bits_per_word = 8;
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+
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+ /*
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+ * baudrate & width will be set ralink_spi_setup_transfer
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+ */
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+ return 0;
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+}
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+
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+static void ralink_spi_reset(struct ralink_spi *rs)
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+{
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+ ralink_spi_write(rs, RAMIPS_SPI_CFG,
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+ SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
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+ SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
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+ ralink_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
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+}
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+
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+static int ralink_spi_probe(struct platform_device *pdev)
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+{
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+ struct spi_master *master;
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+ struct ralink_spi *rs;
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+ struct resource *r;
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+ int status = 0;
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+
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+ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
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+ if (master == NULL) {
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+ dev_dbg(&pdev->dev, "master allocation failed\n");
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+ return -ENOMEM;
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+ }
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+
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+ //if (pdev->id != -1)
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+ master->bus_num = 0;
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+
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+ /* we support only mode 0, and no options */
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+ master->mode_bits = 0;
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+
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+ master->setup = ralink_spi_setup;
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+ master->transfer_one_message = ralink_spi_transfer_one_message;
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+ master->num_chipselect = RALINK_NUM_CHIPSELECTS;
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+ master->dev.of_node = pdev->dev.of_node;
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+
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+ dev_set_drvdata(&pdev->dev, master);
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+
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+ rs = spi_master_get_devdata(master);
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+ rs->master = master;
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+
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+ rs->clk = clk_get(&pdev->dev, NULL);
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+ if (IS_ERR(rs->clk)) {
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+ status = PTR_ERR(rs->clk);
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+ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
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+ status);
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+ goto out_put_master;
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+ }
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+
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+ status = clk_enable(rs->clk);
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+ if (status)
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+ goto out_put_clk;
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+
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+ rs->sys_freq = clk_get_rate(rs->clk);
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+ spi_debug("%s: sys_freq: %u\n", __func__, rs->sys_freq);
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+
|
|
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ if (r == NULL) {
|
|
+ status = -ENODEV;
|
|
+ goto out_disable_clk;
|
|
+ }
|
|
+
|
|
+ rs->base = devm_request_and_ioremap(&pdev->dev, r);
|
|
+ if (!rs->base) {
|
|
+ status = -EADDRNOTAVAIL;
|
|
+ goto out_disable_clk;
|
|
+ }
|
|
+
|
|
+ device_reset(&pdev->dev);
|
|
+
|
|
+ ralink_spi_reset(rs);
|
|
+
|
|
+ status = spi_register_master(master);
|
|
+ if (status)
|
|
+ goto out_disable_clk;
|
|
+
|
|
+ return 0;
|
|
+
|
|
+out_disable_clk:
|
|
+ clk_disable(rs->clk);
|
|
+out_put_clk:
|
|
+ clk_put(rs->clk);
|
|
+out_put_master:
|
|
+ spi_master_put(master);
|
|
+ return status;
|
|
+}
|
|
+
|
|
+static int ralink_spi_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct spi_master *master;
|
|
+ struct ralink_spi *rs;
|
|
+
|
|
+ master = dev_get_drvdata(&pdev->dev);
|
|
+ rs = spi_master_get_devdata(master);
|
|
+
|
|
+ clk_disable(rs->clk);
|
|
+ clk_put(rs->clk);
|
|
+ spi_unregister_master(master);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+MODULE_ALIAS("platform:" DRIVER_NAME);
|
|
+
|
|
+static const struct of_device_id ralink_spi_match[] = {
|
|
+ { .compatible = "ralink,rt2880-spi" },
|
|
+ {},
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, ralink_spi_match);
|
|
+
|
|
+static struct platform_driver ralink_spi_driver = {
|
|
+ .driver = {
|
|
+ .name = DRIVER_NAME,
|
|
+ .owner = THIS_MODULE,
|
|
+ .of_match_table = ralink_spi_match,
|
|
+ },
|
|
+ .probe = ralink_spi_probe,
|
|
+ .remove = ralink_spi_remove,
|
|
+};
|
|
+
|
|
+module_platform_driver(ralink_spi_driver);
|
|
+
|
|
+MODULE_DESCRIPTION("Ralink SPI driver");
|
|
+MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
|
|
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
|
|
+MODULE_LICENSE("GPL");
|
|
--
|
|
1.7.10.4
|
|
|