376 lines
12 KiB
C
376 lines
12 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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*******************************************************************************/
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/*******************************************************************************
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* mvSysHwCfg.h - Marvell system HW configuration file
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*
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* DESCRIPTION:
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* None.
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*
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* DEPENDENCIES:
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* None.
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*
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*******************************************************************************/
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#ifndef __INCmvSysHwConfigh
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#define __INCmvSysHwConfigh
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#include "../../../../include/linux/autoconf.h"
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#define CONFIG_MARVELL 1
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/* includes */
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#define _1K 0x00000400
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#define _4K 0x00001000
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#define _8K 0x00002000
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#define _16K 0x00004000
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#define _32K 0x00008000
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#define _64K 0x00010000
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#define _128K 0x00020000
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#define _256K 0x00040000
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#define _512K 0x00080000
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#define _1M 0x00100000
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#define _2M 0x00200000
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#define _4M 0x00400000
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#define _8M 0x00800000
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#define _16M 0x01000000
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#define _32M 0x02000000
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#define _64M 0x04000000
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#define _128M 0x08000000
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#define _256M 0x10000000
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#define _512M 0x20000000
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#define _1G 0x40000000
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#define _2G 0x80000000
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/****************************************/
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/* Soc supporeted Units definitions */
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/****************************************/
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#ifdef CONFIG_MV_INCLUDE_PEX
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#define MV_INCLUDE_PEX
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#endif
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#ifdef CONFIG_MV_INCLUDE_TWSI
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#define MV_INCLUDE_TWSI
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#endif
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#ifdef CONFIG_MV_INCLUDE_CESA
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#define MV_INCLUDE_CESA
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#endif
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#ifdef CONFIG_MV_INCLUDE_GIG_ETH
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#define MV_INCLUDE_GIG_ETH
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#endif
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#ifdef CONFIG_MV_INCLUDE_INTEG_SATA
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#define MV_INCLUDE_INTEG_SATA
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#define MV_INCLUDE_SATA
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#endif
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#ifdef CONFIG_MV_INCLUDE_USB
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#define MV_INCLUDE_USB
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#define MV_USB_VOLTAGE_FIX
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#endif
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#ifdef CONFIG_MV_INCLUDE_NAND
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#define MV_INCLUDE_NAND
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#endif
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#ifdef CONFIG_MV_INCLUDE_TDM
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#define MV_INCLUDE_TDM
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#endif
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#ifdef CONFIG_MV_INCLUDE_XOR
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#define MV_INCLUDE_XOR
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#endif
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#ifdef CONFIG_MV_INCLUDE_TWSI
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#define MV_INCLUDE_TWSI
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#endif
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#ifdef CONFIG_MV_INCLUDE_UART
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#define MV_INCLUDE_UART
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#endif
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#ifdef CONFIG_MV_INCLUDE_SPI
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#define MV_INCLUDE_SPI
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#endif
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#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD
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#define MV_INCLUDE_SFLASH_MTD
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#endif
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#ifdef CONFIG_MV_INCLUDE_AUDIO
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#define MV_INCLUDE_AUDIO
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#endif
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#ifdef CONFIG_MV_INCLUDE_TS
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#define MV_INCLUDE_TS
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#endif
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#ifdef CONFIG_MV_INCLUDE_SDIO
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#define MV_INCLUDE_SDIO
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#endif
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/* NAND flash stuff */
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#ifdef CONFIG_MV_NAND_BOOT
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#define MV_NAND_BOOT
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#endif
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#ifdef CONFIG_MV_NAND
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#define MV_NAND
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#endif
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/* SPI flash stuff */
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#ifdef CONFIG_MV_SPI_BOOT
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#define MV_SPI_BOOT
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#endif
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/****************************************************************/
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/************* General configuration ********************/
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/****************************************************************/
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/* Enable Clock Power Control */
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#define MV_INCLUDE_CLK_PWR_CNTRL
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/* Disable the DEVICE BAR in the PEX */
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#define MV_DISABLE_PEX_DEVICE_BAR
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/* Allow the usage of early printings during initialization */
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#define MV_INCLUDE_EARLY_PRINTK
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/****************************************************************/
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/************* NFP configuration ********************************/
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/****************************************************************/
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#define MV_NFP_SEC_Q_SIZE 64
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#define MV_NFP_SEC_REQ_Q_SIZE 1000
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/****************************************************************/
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/************* CESA configuration ********************/
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/****************************************************************/
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#ifdef MV_INCLUDE_CESA
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#define MV_CESA_MAX_CHAN 4
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/* Use 2K of SRAM */
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#define MV_CESA_MAX_BUF_SIZE 1600
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#endif /* MV_INCLUDE_CESA */
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#if defined(CONFIG_MV_INCLUDE_GIG_ETH)
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#ifdef CONFIG_MV_NFP_STATS
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#define MV_FP_STATISTICS
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#else
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#undef MV_FP_STATISTICS
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#endif
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/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */
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#define MV_ETH_SKB_REUSE_DEFAULT 1
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/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */
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#define MV_ETH_TX_EN_DEFAULT 0
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/* un-comment if you want to perform tx_done from within the poll function */
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/* #define ETH_TX_DONE_ISR */
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/* put descriptors in uncached memory */
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/* #define ETH_DESCR_UNCACHED */
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/* Descriptors location: DRAM/internal-SRAM */
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#define ETH_DESCR_IN_SDRAM
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#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */
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#if defined(ETH_DESCR_IN_SRAM)
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#if defined(ETH_DESCR_UNCACHED)
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#define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM"
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#else
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#define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM"
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#endif
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#elif defined(ETH_DESCR_IN_SDRAM)
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#if defined(ETH_DESCR_UNCACHED)
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#define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM"
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#else
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#define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM"
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#endif
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#else
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#error "Ethernet descriptors location undefined"
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#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/
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/* SW Sync-Barrier: not relevant for 88fxx81*/
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/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */
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/* In RX the CPU theoretically might see himself as the descriptor owner, */
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/* although the buffer hadn't been written to DRAM yet. Performance cost. */
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/* #define INCLUDE_SYNC_BARR */
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/* Buffers cache coherency method (buffers in DRAM) */
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#ifndef MV_CACHE_COHER_SW
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/* Taken from mvCommon.h */
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/* Memory uncached, HW or SW cache coherency is not needed */
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#define MV_UNCACHED 0
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/* Memory cached, HW cache coherency supported in WriteThrough mode */
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#define MV_CACHE_COHER_HW_WT 1
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/* Memory cached, HW cache coherency supported in WriteBack mode */
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#define MV_CACHE_COHER_HW_WB 2
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/* Memory cached, No HW cache coherency, Cache coherency must be in SW */
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#define MV_CACHE_COHER_SW 3
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#endif
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/* DRAM cache coherency configuration */
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#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW
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#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */
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#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB)
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#define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)"
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#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT)
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#define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)"
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#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW)
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#define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency"
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#elif (ETHER_DRAM_COHER == MV_UNCACHED)
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# define ETH_SDRAM_CONFIG_STR "DRAM uncached"
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#else
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#error "Ethernet-DRAM undefined"
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#endif /* ETHER_DRAM_COHER */
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/****************************************************************/
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/************* Ethernet driver configuration ********************/
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/****************************************************************/
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/* port's default queueus */
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#define ETH_DEF_TXQ 0
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#define ETH_DEF_RXQ 0
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#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM
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#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM
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/* interrupt coalescing setting */
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#define ETH_TX_COAL 200
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#define ETH_RX_COAL 200
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/* Checksum offloading */
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#define TX_CSUM_OFFLOAD
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#define RX_CSUM_OFFLOAD
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#endif /* CONFIG_MV_INCLUDE_GIG_ETH */
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/****************************************************************/
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/*************** Telephony configuration ************************/
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/****************************************************************/
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#if defined(CONFIG_MV_TDM_LINEAR_MODE)
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#define MV_TDM_LINEAR_MODE
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#elif defined(CONFIG_MV_TDM_ULAW_MODE)
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#define MV_TDM_ULAW_MODE
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#endif
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#if defined(CONFIG_MV_TDM_5CHANNELS)
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#define MV_TDM_5CHANNELS
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#endif
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#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE)
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#define MV_TDM_USE_EXTERNAL_PCLK_SOURCE
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#endif
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/* We use the following registers to store DRAM interface pre configuration */
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/* auto-detection results */
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/* IMPORTANT: We are using mask register for that purpose. Before writing */
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/* to units mask register, make sure main maks register is set to disable */
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/* all interrupts. */
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#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */
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#define DRAM_BUF_REG1 0x30820 /* sdram config */
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#define DRAM_BUF_REG2 0x30830 /* sdram mode */
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#define DRAM_BUF_REG3 0x308c4 /* dunit control low */
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#define DRAM_BUF_REG4 0x60a90 /* sdram address control */
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#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */
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#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */
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#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */
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#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */
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#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */
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#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */
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#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */
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#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */
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#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */
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#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */
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/* Following the pre-configuration registers default values restored after */
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/* auto-detection is done */
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#define DRAM_BUF_REG_DV 0
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/* System Mapping */
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#define SDRAM_CS0_BASE 0x00000000
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#define SDRAM_CS0_SIZE _256M
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#define SDRAM_CS1_BASE 0x10000000
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#define SDRAM_CS1_SIZE _256M
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#define SDRAM_CS2_BASE 0x20000000
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#define SDRAM_CS2_SIZE _256M
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#define SDRAM_CS3_BASE 0x30000000
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#define SDRAM_CS3_SIZE _256M
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/* PEX */
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#define PEX0_MEM_BASE 0xe8000000
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#define PEX0_MEM_SIZE _128M
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#define PEX0_IO_BASE 0xf2000000
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#define PEX0_IO_SIZE _1M
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/* Device Chip Selects */
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#define NFLASH_CS_BASE 0xfa000000
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#define NFLASH_CS_SIZE _2M
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#define SPI_CS_BASE 0xf4000000
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#define SPI_CS_SIZE _16M
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#define CRYPT_ENG_BASE 0xf0000000
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#define CRYPT_ENG_SIZE _2M
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#define BOOTDEV_CS_BASE 0xff800000
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#define BOOTDEV_CS_SIZE _8M
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/* CS2 - BOOTROM */
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#define DEVICE_CS2_BASE 0xff900000
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#define DEVICE_CS2_SIZE _1M
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/* PEX Work arround */
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/* the target we will use for the workarround */
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#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM
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/*a flag that indicates if we are going to use the
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size and base of the target we using for the workarround
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window */
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#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1
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/* if the above flag is 0 then the following values
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will be used for the workarround window base and size,
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otherwise the following defines will be ignored */
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#define PEX_CONFIG_RW_WA_BASE 0xF3000000
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#define PEX_CONFIG_RW_WA_SIZE _16M
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/* Internal registers: size is defined in Controllerenvironment */
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#define INTER_REGS_BASE 0xFEE00000
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/* DRAM detection stuff */
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#define MV_DRAM_AUTO_SIZE
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/* Board clock detection */
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#define TCLK_AUTO_DETECT /* Use Tclk auto detection */
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#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */
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#define PCLCK_AUTO_DETECT /* Use PClk auto detection */
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#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */
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/* PEX-PCI\PCI-PCI Bridge*/
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#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/
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#endif /* __INCmvSysHwConfigh */
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