138 lines
2.9 KiB
C
138 lines
2.9 KiB
C
/*
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* Ralink RT305x SoC specific setup
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/serial_8250.h>
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#include <asm/bootinfo.h>
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#include <asm/mips_machine.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/mach-ralink/rt305x.h>
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#include <asm/mach-ralink/rt305x_regs.h>
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#include "machine.h"
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enum rt305x_mach_type rt305x_mach;
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static void rt305x_restart(char *command)
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{
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rt305x_sysc_wr(RT305X_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
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while (1)
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if (cpu_wait)
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cpu_wait();
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}
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static void rt305x_halt(void)
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{
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while (1)
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if (cpu_wait)
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cpu_wait();
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}
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static void __init rt305x_detect_mem_size(void)
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{
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unsigned long size;
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for (size = RT305X_MEM_SIZE_MIN; size < RT305X_MEM_SIZE_MAX;
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size <<= 1 ) {
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if (!memcmp(rt305x_detect_mem_size,
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rt305x_detect_mem_size + size, 1024))
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break;
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}
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add_memory_region(RT305X_SDRAM_BASE, size, BOOT_MEM_RAM);
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}
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static void __init rt305x_early_serial_setup(void)
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{
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struct uart_port p;
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int err;
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memset(&p, 0, sizeof(p));
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p.flags = UPF_SKIP_TEST;
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p.iotype = UPIO_AU;
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p.uartclk = rt305x_sys_freq;
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p.regshift = 2;
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p.type = PORT_16550A;
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p.mapbase = RT305X_UART0_BASE;
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p.membase = ioremap_nocache(p.mapbase, RT305X_UART0_SIZE);
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p.line = 0;
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p.irq = RT305X_INTC_IRQ_UART0;
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err = early_serial_setup(&p);
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if (err)
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printk(KERN_ERR "RT305x: early UART0 registration failed %d\n",
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err);
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p.mapbase = RT305X_UART1_BASE;
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p.membase = ioremap_nocache(p.mapbase, RT305X_UART1_SIZE);
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p.line = 1;
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p.irq = RT305X_INTC_IRQ_UART1;
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err = early_serial_setup(&p);
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if (err)
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printk(KERN_ERR "RT305x: early UART1 registration failed %d\n",
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err);
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}
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const char *get_system_type(void)
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{
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return rt305x_sys_type;
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}
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unsigned int __cpuinit get_c0_compare_irq(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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void __init plat_mem_setup(void)
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{
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set_io_port_base(KSEG1);
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rt305x_intc_base = ioremap_nocache(RT305X_INTC_BASE, PAGE_SIZE);
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rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE);
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rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE);
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rt305x_detect_mem_size();
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rt305x_detect_sys_type();
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rt305x_detect_sys_freq();
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printk(KERN_INFO "%s running at %lu.%02lu MHz\n", get_system_type(),
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rt305x_cpu_freq / 1000000,
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(rt305x_cpu_freq % 1000000) * 100 / 1000000);
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_machine_restart = rt305x_restart;
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_machine_halt = rt305x_halt;
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pm_power_off = rt305x_halt;
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rt305x_early_serial_setup();
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}
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void __init plat_time_init(void)
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{
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mips_hpt_frequency = rt305x_cpu_freq / 2;
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}
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static int __init rt305x_machine_setup(void)
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{
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mips_machine_setup(rt305x_mach);
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return 0;
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}
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arch_initcall(rt305x_machine_setup);
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