0206a400cf
This patch improves the default configuration of DWC2 on lantiq SoCs somewhat: * Set maximum packet count to largest allowed value by the DWC2 (511) * Use 16-bit DMA bursts * Divide fifo buffers more evenly Default fifo buffer sizes from original ltq-hcd driver seem really irrational. For example according to DWC2 data book rxfifo size of 240 will not fit even a single full length USB packet. On the other hand non-periodic tx fifo size of 240 is more than enough to fit one complete packet. Change the sizes around to improve the situation and to fix some issues especially with isochronous USB transfers. Signed-off-by: Antti Seppälä <a.seppala@gmail.com> SVN-Revision: 47563 |
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| .. | ||
| imagebuilder | ||
| linux | ||
| sdk | ||
| toolchain | ||
| Config.in | ||
| Makefile | ||