365 lines
11 KiB
C
365 lines
11 KiB
C
#ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
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#define IFXMIPS_ATM_FW_REGS_COMMON_H
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#if defined(CONFIG_DANUBE)
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#include "ifxmips_atm_fw_regs_danube.h"
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#elif defined(CONFIG_AMAZON_SE)
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#include "ifxmips_atm_fw_regs_amazon_se.h"
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#elif defined(CONFIG_AR9)
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#include "ifxmips_atm_fw_regs_ar9.h"
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#elif defined(CONFIG_VR9)
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#include "ifxmips_atm_fw_regs_vr9.h"
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#else
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#error Platform is not specified!
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#endif
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/*
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* PPE ATM Cell Header
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*/
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#if defined(__BIG_ENDIAN)
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struct uni_cell_header {
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unsigned int gfc :4;
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unsigned int vpi :8;
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unsigned int vci :16;
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unsigned int pti :3;
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unsigned int clp :1;
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};
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#else
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struct uni_cell_header {
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unsigned int clp :1;
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unsigned int pti :3;
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unsigned int vci :16;
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unsigned int vpi :8;
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unsigned int gfc :4;
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};
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#endif // defined(__BIG_ENDIAN)
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/*
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* Inband Header and Trailer
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*/
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#if defined(__BIG_ENDIAN)
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struct rx_inband_trailer {
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/* 0 - 3h */
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unsigned int uu :8;
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unsigned int cpi :8;
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unsigned int stw_res1:4;
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unsigned int stw_clp :1;
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unsigned int stw_ec :1;
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unsigned int stw_uu :1;
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unsigned int stw_cpi :1;
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unsigned int stw_ovz :1;
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unsigned int stw_mfl :1;
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unsigned int stw_usz :1;
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unsigned int stw_crc :1;
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unsigned int stw_il :1;
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unsigned int stw_ra :1;
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unsigned int stw_res2:2;
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/* 4 - 7h */
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unsigned int gfc :4;
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unsigned int vpi :8;
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unsigned int vci :16;
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unsigned int pti :3;
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unsigned int clp :1;
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};
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struct tx_inband_header {
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/* 0 - 3h */
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unsigned int gfc :4;
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unsigned int vpi :8;
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unsigned int vci :16;
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unsigned int pti :3;
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unsigned int clp :1;
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/* 4 - 7h */
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unsigned int uu :8;
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unsigned int cpi :8;
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unsigned int pad :8;
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unsigned int res1 :8;
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};
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#else
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struct rx_inband_trailer {
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/* 0 - 3h */
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unsigned int stw_res2:2;
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unsigned int stw_ra :1;
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unsigned int stw_il :1;
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unsigned int stw_crc :1;
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unsigned int stw_usz :1;
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unsigned int stw_mfl :1;
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unsigned int stw_ovz :1;
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unsigned int stw_cpi :1;
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unsigned int stw_uu :1;
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unsigned int stw_ec :1;
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unsigned int stw_clp :1;
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unsigned int stw_res1:4;
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unsigned int cpi :8;
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unsigned int uu :8;
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/* 4 - 7h */
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unsigned int clp :1;
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unsigned int pti :3;
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unsigned int vci :16;
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unsigned int vpi :8;
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unsigned int gfc :4;
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};
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struct tx_inband_header {
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/* 0 - 3h */
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unsigned int clp :1;
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unsigned int pti :3;
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unsigned int vci :16;
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unsigned int vpi :8;
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unsigned int gfc :4;
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/* 4 - 7h */
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unsigned int res1 :8;
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unsigned int pad :8;
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unsigned int cpi :8;
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unsigned int uu :8;
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};
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#endif // defined(__BIG_ENDIAN)
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/*
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* MIB Table Maintained by Firmware
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*/
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struct wan_mib_table {
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u32 res1;
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u32 wrx_drophtu_cell;
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u32 wrx_dropdes_pdu;
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u32 wrx_correct_pdu;
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u32 wrx_err_pdu;
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u32 wrx_dropdes_cell;
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u32 wrx_correct_cell;
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u32 wrx_err_cell;
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u32 wrx_total_byte;
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u32 res2;
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u32 wtx_total_pdu;
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u32 wtx_total_cell;
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u32 wtx_total_byte;
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};
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/*
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* Host-PPE Communication Data Structure
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*/
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#if defined(__BIG_ENDIAN)
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struct wrx_queue_config {
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/* 0h */
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unsigned int res2 :27;
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unsigned int dmach :4;
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unsigned int errdp :1;
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/* 1h */
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unsigned int oversize :16;
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unsigned int undersize :16;
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/* 2h */
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unsigned int res1 :16;
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unsigned int mfs :16;
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/* 3h */
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unsigned int uumask :8;
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unsigned int cpimask :8;
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unsigned int uuexp :8;
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unsigned int cpiexp :8;
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};
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struct wtx_port_config {
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unsigned int res1 :27;
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unsigned int qid :4;
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unsigned int qsben :1;
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};
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struct wtx_queue_config {
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unsigned int res1 :25;
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unsigned int sbid :1;
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unsigned int res2 :3;
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unsigned int type :2;
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unsigned int qsben :1;
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};
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struct wrx_dma_channel_config {
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/* 0h */
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unsigned int res1 :1;
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unsigned int mode :2;
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unsigned int rlcfg :1;
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unsigned int desba :28;
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/* 1h */
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unsigned int chrl :16;
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unsigned int clp1th :16;
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/* 2h */
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unsigned int deslen :16;
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unsigned int vlddes :16;
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};
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struct wtx_dma_channel_config {
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/* 0h */
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unsigned int res2 :1;
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unsigned int mode :2;
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unsigned int res3 :1;
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unsigned int desba :28;
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/* 1h */
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unsigned int res1 :32;
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/* 2h */
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unsigned int deslen :16;
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unsigned int vlddes :16;
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};
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struct htu_entry {
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unsigned int res1 :1;
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unsigned int clp :1;
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unsigned int pid :2;
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unsigned int vpi :8;
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unsigned int vci :16;
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unsigned int pti :3;
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unsigned int vld :1;
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};
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struct htu_mask {
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unsigned int set :1;
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unsigned int clp :1;
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unsigned int pid_mask :2;
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unsigned int vpi_mask :8;
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unsigned int vci_mask :16;
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unsigned int pti_mask :3;
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unsigned int clear :1;
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};
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struct htu_result {
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unsigned int res1 :12;
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unsigned int cellid :4;
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unsigned int res2 :5;
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unsigned int type :1;
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unsigned int ven :1;
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unsigned int res3 :5;
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unsigned int qid :4;
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};
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struct rx_descriptor {
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/* 0 - 3h */
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unsigned int own :1;
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unsigned int c :1;
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unsigned int sop :1;
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unsigned int eop :1;
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unsigned int res1 :3;
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unsigned int byteoff :2;
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unsigned int res2 :2;
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unsigned int id :4;
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unsigned int err :1;
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unsigned int datalen :16;
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/* 4 - 7h */
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unsigned int res3 :4;
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unsigned int dataptr :28;
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};
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struct tx_descriptor {
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/* 0 - 3h */
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unsigned int own :1;
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unsigned int c :1;
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unsigned int sop :1;
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unsigned int eop :1;
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unsigned int byteoff :5;
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unsigned int res1 :5;
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unsigned int iscell :1;
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unsigned int clp :1;
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unsigned int datalen :16;
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/* 4 - 7h */
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unsigned int res2 :4;
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unsigned int dataptr :28;
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};
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#else
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struct wrx_queue_config {
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/* 0h */
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unsigned int errdp :1;
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unsigned int dmach :4;
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unsigned int res2 :27;
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/* 1h */
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unsigned int undersize :16;
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unsigned int oversize :16;
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/* 2h */
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unsigned int mfs :16;
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unsigned int res1 :16;
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/* 3h */
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unsigned int cpiexp :8;
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unsigned int uuexp :8;
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unsigned int cpimask :8;
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unsigned int uumask :8;
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};
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struct wtx_port_config {
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unsigned int qsben :1;
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unsigned int qid :4;
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unsigned int res1 :27;
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};
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struct wtx_queue_config {
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unsigned int qsben :1;
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unsigned int type :2;
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unsigned int res2 :3;
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unsigned int sbid :1;
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unsigned int res1 :25;
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};
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struct wrx_dma_channel_config
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{
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/* 0h */
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unsigned int desba :28;
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unsigned int rlcfg :1;
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unsigned int mode :2;
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unsigned int res1 :1;
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/* 1h */
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unsigned int clp1th :16;
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unsigned int chrl :16;
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/* 2h */
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unsigned int vlddes :16;
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unsigned int deslen :16;
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};
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struct wtx_dma_channel_config {
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/* 0h */
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unsigned int desba :28;
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unsigned int res3 :1;
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unsigned int mode :2;
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unsigned int res2 :1;
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/* 1h */
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unsigned int res1 :32;
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/* 2h */
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unsigned int vlddes :16;
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unsigned int deslen :16;
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};
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struct rx_descriptor {
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/* 4 - 7h */
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unsigned int dataptr :28;
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unsigned int res3 :4;
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/* 0 - 3h */
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unsigned int datalen :16;
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unsigned int err :1;
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unsigned int id :4;
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unsigned int res2 :2;
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unsigned int byteoff :2;
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unsigned int res1 :3;
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unsigned int eop :1;
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unsigned int sop :1;
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unsigned int c :1;
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unsigned int own :1;
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};
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struct tx_descriptor {
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/* 4 - 7h */
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unsigned int dataptr :28;
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unsigned int res2 :4;
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/* 0 - 3h */
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unsigned int datalen :16;
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unsigned int clp :1;
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unsigned int iscell :1;
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unsigned int res1 :5;
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unsigned int byteoff :5;
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unsigned int eop :1;
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unsigned int sop :1;
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unsigned int c :1;
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unsigned int own :1;
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};
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#endif // defined(__BIG_ENDIAN)
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#endif // IFXMIPS_ATM_FW_REGS_COMMON_H
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