4ff6c43499
This commit finally adds support for the built in SD/MMC controller in IPQ4019 SoC. Controller is supported by the upstream SDHCI-MSM driver with a minor clock setting patch. Patch is special to the IPQ4019 and cannot be upstreamed. LDO and SDHCI node are upstreamed, and LDO node is awaiting to be accepted. Signed-off-by: Robert Marko <robimarko@gmail.com>
47 lines
1.3 KiB
Diff
47 lines
1.3 KiB
Diff
From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
|
|
From: Christian Lamparter <chunkeey@gmail.com>
|
|
Date: Sun, 20 Nov 2016 02:20:54 +0100
|
|
Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
|
|
|
|
This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
|
|
nodes which are needed for the ar40xx.c driver to initialize the
|
|
switch.
|
|
|
|
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|
---
|
|
arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
|
|
1 file changed, 23 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
@@ -616,6 +616,29 @@
|
|
};
|
|
};
|
|
|
|
+ ess-switch@c000000 {
|
|
+ compatible = "qcom,ess-switch";
|
|
+ reg = <0xc000000 0x80000>;
|
|
+ switch_access_mode = "local bus";
|
|
+ resets = <&gcc ESS_RESET>;
|
|
+ reset-names = "ess_rst";
|
|
+ clocks = <&gcc GCC_ESS_CLK>;
|
|
+ clock-names = "ess_clk";
|
|
+ switch_cpu_bmp = <0x1>;
|
|
+ switch_lan_bmp = <0x1e>;
|
|
+ switch_wan_bmp = <0x20>;
|
|
+ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
|
|
+ switch_initvlas = <0x7c 0x54>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ess-psgmii@98000 {
|
|
+ compatible = "qcom,ess-psgmii";
|
|
+ reg = <0x98000 0x800>;
|
|
+ psgmii_access_mode = "local bus";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
usb3_ss_phy: ssphy@9a000 {
|
|
compatible = "qcom,usb-ss-ipq4019-phy";
|
|
#phy-cells = <0>;
|