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ipq806x: dwmac: clear forced speed during probe

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On a Ubiquiti UniFi AC HD (ubnt,unifi-ac-hd, UAP-AC-HD, UAP301), a
forced speed on gmac1 is set in the QSGMII PCS_ALL_CH_CTL register,
presumably by the bootloader (4.3.28), preventing the interface from
being usable. The QSDK NSS GMAC driver takes care to clear the forced
speed in nss_gmac_qsgmii_dev_init
(https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-gmac/tree/ipq806x/nss_gmac_init.c?h=nss
at d5bb14925861).

gmac1 is connected to the port on the device labeled SECONDARY, and is
currently eth0 but will be switched to eth1 by a subsequent patch. By
clearing the QSGMII PCS forced speed during dwmac initialization when
SGMII is in use, this port becomes usable.

This patch is upstreamable, and will be sent upstream after successful
testing in OpenWrt.

Signed-off-by: Mark Mentovai <mark@moxienet.com>
Build-tested: ipq806x/ubnt,unifi-ac-hd
Run-tested: ipq806x/ubnt,unifi-ac-hd
This commit is contained in:
Mark Mentovai 2021-04-12 11:59:18 -04:00 committed by Petr Štetiar
parent ed4641e9f1
commit fa731838c5
1 changed files with 33 additions and 0 deletions
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33
target/linux/ipq806x/patches-5.4/100-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch Normal file
View File

@ -0,0 +1,33 @@
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
@@ -64,6 +64,17 @@
#define NSS_COMMON_CLK_DIV_SGMII_100 4
#define NSS_COMMON_CLK_DIV_SGMII_10 49
+#define QSGMII_PCS_ALL_CH_CTL 0x80
+#define QSGMII_PCS_CH_SPEED_FORCE 0x2
+#define QSGMII_PCS_CH_SPEED_10 0x0
+#define QSGMII_PCS_CH_SPEED_100 0x4
+#define QSGMII_PCS_CH_SPEED_1000 0x8
+#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \
+ QSGMII_PCS_CH_SPEED_10 | \
+ QSGMII_PCS_CH_SPEED_100 | \
+ QSGMII_PCS_CH_SPEED_1000)
+#define QSGMII_PCS_CH_SPEED_SHIFT(x) (x * 4)
+
#define QSGMII_PCS_CAL_LCKDT_CTL 0x120
#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19)
@@ -345,6 +356,12 @@ static int ipq806x_gmac_probe(struct pla
0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);
+
+ regmap_update_bits(gmac->qsgmii_csr,
+ QSGMII_PCS_ALL_CH_CTL,
+ QSGMII_PCS_CH_SPEED_MASK <<
+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id),
+ 0);
}
plat_dat->has_gmac = true;