lantiq: 4.19: increase usb reset timeouts
With kernel 4.19 dwc2 would not want to initialize due to reset timeouts, while it worked fine with 4.14. Increase the reset timeouts to 1 second, as it was used by the old lantiq ifxhcd usb driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Mathias Kresin <dev@kresin.me>
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From bfe92b01cafebb10f0d7f38dceb37433687b7887 Mon Sep 17 00:00:00 2001
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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Date: Thu, 20 Jun 2019 19:50:22 +0200
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Subject: [PATCH] usb: dwc2: use a longer AHB idle timeout in dwc2_core_reset()
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Use a 10000us AHB idle timeout in dwc2_core_reset() and make it
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consistent with the other "wait for AHB master IDLE state" ocurrences.
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This fixes a problem for me where dwc2 would not want to initialize when
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updating to 4.19 on a MIPS Lantiq VRX200 SoC. dwc2 worked fine with
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4.14.
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Testing on my board shows that it takes 180us until AHB master IDLE
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state is signalled. The very old vendor driver for this SoC (ifxhcd)
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used a 1 second timeout.
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Use the same timeout that is used everywhere when polling for
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GRSTCTL_AHBIDLE instead of using a timeout that "works for one board"
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(180us in my case) to have consistent behavior across the dwc2 driver.
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Cc: linux-stable <stable@vger.kernel.org> # 4.19+
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Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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---
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drivers/usb/dwc2/core.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/usb/dwc2/core.c
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+++ b/drivers/usb/dwc2/core.c
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@@ -531,7 +531,7 @@ int dwc2_core_reset(struct dwc2_hsotg *h
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}
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/* Wait for AHB master IDLE state */
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- if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 50)) {
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+ if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
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dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
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__func__);
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return -EBUSY;
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@ -0,0 +1,29 @@
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From 09bbf8c732e7a6ce290fc7c2d5a3e79ec6c3e8d2 Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Wed, 3 Jul 2019 17:03:02 +0200
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Subject: [PATCH] usb: dwc2: use a longer core rest timeout in
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dwc2_core_reset()
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Testing on different generations of Lantiq MIPS SoC based boards, showed
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that it takes up to 1500 us until the core reset bit is cleared.
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The driver from the vendor SDK (ifxhcd) uses a 1 second timeout. Use the
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same timeout to fix wrong hang detections and make the driver work for
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Lantiq MIPS SoCs.
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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drivers/usb/dwc2/core.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/usb/dwc2/core.c
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+++ b/drivers/usb/dwc2/core.c
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@@ -524,7 +524,7 @@ int dwc2_core_reset(struct dwc2_hsotg *h
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greset |= GRSTCTL_CSFTRST;
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dwc2_writel(hsotg, greset, GRSTCTL);
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- if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) {
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+ if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 10000)) {
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dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n",
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__func__);
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return -EBUSY;
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