oxnas: cleanup and improve pcie driver
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
parent
068c4cf407
commit
dcb08049ae
@ -11,263 +11,24 @@
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/mbus.h>
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#include <linux/mfd/syscon.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#define OXNAS_UART1_BASE 0x44200000
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#define OXNAS_UART1_SIZE SZ_32
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#define OXNAS_UART1_BASE_VA 0xF0000000
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#define OXNAS_UART2_BASE 0x44300000
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#define OXNAS_UART2_SIZE SZ_32
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#define OXNAS_PERCPU_BASE 0x47000000
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#define OXNAS_PERCPU_SIZE SZ_8K
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#define OXNAS_PERCPU_BASE_VA 0xF0002000
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#define OXNAS_SYSCRTL_BASE 0x44E00000
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#define OXNAS_SYSCRTL_SIZE SZ_4K
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#define OXNAS_SYSCRTL_BASE_VA 0xF0004000
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#define OXNAS_SECCRTL_BASE 0x44F00000
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#define OXNAS_SECCRTL_SIZE SZ_4K
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#define OXNAS_SECCRTL_BASE_VA 0xF0005000
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#define OXNAS_RPSA_BASE 0x44400000
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#define OXNAS_RPSA_SIZE SZ_4K
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#define OXNAS_RPSA_BASE_VA 0xF0006000
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#define OXNAS_RPSC_BASE 0x44500000
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#define OXNAS_RPSC_SIZE SZ_4K
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#define OXNAS_RPSC_BASE_VA 0xF0007000
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/*
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* Location of flags and vectors in SRAM for controlling the booting of the
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* secondary ARM11 processors.
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*/
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#define OXNAS_SCU_BASE_VA OXNAS_PERCPU_BASE_VA
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#define OXNAS_GICN_BASE_VA(n) (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100)
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#define HOLDINGPEN_CPU IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
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#define HOLDINGPEN_LOCATION IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
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/**
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* System block reset and clock control
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*/
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#define SYS_CTRL_PCI_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20)
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#define SYSCTRL_CLK_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24)
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#define SYS_CTRL_CLK_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C)
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#define SYS_CTRL_CLK_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30)
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#define SYS_CTRL_RST_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34)
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#define SYS_CTRL_RST_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38)
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#define SYS_CTRL_PLLSYS_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48)
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#define SYS_CTRL_CLK_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64)
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#define SYS_CTRL_PLLSYS_KEY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C)
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#define SYS_CTRL_GMAC_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78)
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#define SYS_CTRL_GMAC_DELAY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100)
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/* Scratch registers */
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#define SYS_CTRL_SCRATCHWORD0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
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#define SYS_CTRL_SCRATCHWORD1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
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#define SYS_CTRL_SCRATCHWORD2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc)
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#define SYS_CTRL_SCRATCHWORD3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0)
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#define SYS_CTRL_PLLA_CTRL0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0)
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#define SYS_CTRL_PLLA_CTRL1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4)
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#define SYS_CTRL_PLLA_CTRL2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8)
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#define SYS_CTRL_PLLA_CTRL3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC)
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#define SYS_CTRL_USBHSMPH_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40)
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#define SYS_CTRL_USBHSMPH_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44)
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#define SYS_CTRL_REF300_DIV IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8)
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#define SYS_CTRL_USBHSPHY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84)
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#define SYS_CTRL_USB_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90)
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/* pcie */
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#define SYS_CTRL_HCSL_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114)
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/* System control multi-function pin function selection */
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#define SYS_CTRL_SECONDARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14)
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#define SYS_CTRL_TERTIARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c)
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#define SYS_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94)
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#define SYS_CTRL_DEBUG_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c)
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#define SYS_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4)
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#define SYS_CTRL_PULLUP_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac)
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/* Secure control multi-function pin function selection */
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#define SEC_CTRL_SECONDARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14)
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#define SEC_CTRL_TERTIARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c)
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#define SEC_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94)
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#define SEC_CTRL_DEBUG_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c)
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#define SEC_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4)
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#define SEC_CTRL_PULLUP_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac)
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#define SEC_CTRL_COPRO_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68)
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#define SEC_CTRL_SECURE_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98)
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#define SEC_CTRL_LEON_DEBUG IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0)
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#define SEC_CTRL_PLLB_DIV_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8)
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#define SEC_CTRL_PLLB_CTRL0 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0)
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#define SEC_CTRL_PLLB_CTRL1 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
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#define SEC_CTRL_PLLB_CTRL8 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
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#define RPSA_IRQ_SOFT IOMEM(OXNAS_RPSA_BASE_VA + 0x10)
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#define RPSA_FIQ_ENABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x108)
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#define RPSA_FIQ_DISABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x10C)
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#define RPSA_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC)
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#define RPSC_IRQ_SOFT IOMEM(OXNAS_RPSC_BASE_VA + 0x10)
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#define RPSC_FIQ_ENABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x108)
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#define RPSC_FIQ_DISABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x10C)
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#define RPSC_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC)
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#define RPSA_TIMER2_VAL IOMEM(OXNAS_RPSA_BASE_VA + 0x224)
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#define REF300_DIV_INT_SHIFT 8
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#define REF300_DIV_FRAC_SHIFT 0
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#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
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#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
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#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
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#define USBHSPHY_SUSPENDM_MANUAL_STATE 15
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#define USBHSPHY_ATE_ESET 14
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#define USBHSPHY_TEST_DIN 6
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#define USBHSPHY_TEST_ADD 2
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#define USBHSPHY_TEST_DOUT_SEL 1
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#define USBHSPHY_TEST_CLK 0
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#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
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#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
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#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
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#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
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#define USBAMUX_DEVICE BIT(4)
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#define USBPHY_REFCLKDIV_SHIFT 2
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#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
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#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
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#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
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#define USB_CTRL_USB_CKO_SEL_BIT 0
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#define USB_INT_CLK_XTAL 0
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#define USB_INT_CLK_REF300 2
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#define USB_INT_CLK_PLLB 3
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#define SYS_CTRL_GMAC_CKEN_RX_IN 14
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#define SYS_CTRL_GMAC_CKEN_RXN_OUT 13
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#define SYS_CTRL_GMAC_CKEN_RX_OUT 12
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#define SYS_CTRL_GMAC_CKEN_TX_IN 10
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#define SYS_CTRL_GMAC_CKEN_TXN_OUT 9
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#define SYS_CTRL_GMAC_CKEN_TX_OUT 8
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#define SYS_CTRL_GMAC_RX_SOURCE 7
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#define SYS_CTRL_GMAC_TX_SOURCE 6
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#define SYS_CTRL_GMAC_LOW_TX_SOURCE 4
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#define SYS_CTRL_GMAC_AUTO_TX_SOURCE 3
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#define SYS_CTRL_GMAC_RGMII 2
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#define SYS_CTRL_GMAC_SIMPLE_MUX 1
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#define SYS_CTRL_GMAC_CKEN_GTX 0
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#define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT 0
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#define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT 8
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#define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT 16
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#define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT 24
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#define SYS_CTRL_GMAC_TX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TX_VARDELAY_SHIFT)
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#define SYS_CTRL_GMAC_TXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT)
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#define SYS_CTRL_GMAC_RX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RX_VARDELAY_SHIFT)
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#define SYS_CTRL_GMAC_RXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT)
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#define PLLB_BYPASS 1
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#define PLLB_ENSAT 3
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#define PLLB_OUTDIV 4
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#define PLLB_REFDIV 8
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#define PLLB_DIV_INT_SHIFT 8
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#define PLLB_DIV_FRAC_SHIFT 0
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#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
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#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
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#define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0
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#define SYS_CTRL_CKCTRL_SLOW_BIT 8
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#define SYS_CTRL_UART2_DEQ_EN 0
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#define SYS_CTRL_UART3_DEQ_EN 1
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#define SYS_CTRL_UART3_IQ_EN 2
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#define SYS_CTRL_UART4_IQ_EN 3
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#define SYS_CTRL_UART4_NOT_PCI_MODE 4
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#define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT 11
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#define PLLA_REFDIV_MASK 0x3F
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#define PLLA_REFDIV_SHIFT 8
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#define PLLA_OUTDIV_MASK 0x7
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#define PLLA_OUTDIV_SHIFT 4
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/* bit numbers of clock control register */
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#define SYS_CTRL_CLK_COPRO 0
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#define SYS_CTRL_CLK_DMA 1
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#define SYS_CTRL_CLK_CIPHER 2
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#define SYS_CTRL_CLK_SD 3
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#define SYS_CTRL_CLK_SATA 4
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#define SYS_CTRL_CLK_I2S 5
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#define SYS_CTRL_CLK_USBHS 6
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#define SYS_CTRL_CLK_MACA 7
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#define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA
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#define SYS_CTRL_CLK_PCIEA 8
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#define SYS_CTRL_CLK_STATIC 9
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#define SYS_CTRL_CLK_MACB 10
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#define SYS_CTRL_CLK_PCIEB 11
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#define SYS_CTRL_CLK_REF600 12
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#define SYS_CTRL_CLK_USBDEV 13
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#define SYS_CTRL_CLK_DDR 14
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#define SYS_CTRL_CLK_DDRPHY 15
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#define SYS_CTRL_CLK_DDRCK 16
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/* bit numbers of reset control register */
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#define SYS_CTRL_RST_SCU 0
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#define SYS_CTRL_RST_COPRO 1
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#define SYS_CTRL_RST_ARM0 2
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#define SYS_CTRL_RST_ARM1 3
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#define SYS_CTRL_RST_USBHS 4
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#define SYS_CTRL_RST_USBHSPHYA 5
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#define SYS_CTRL_RST_MACA 6
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#define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
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#define SYS_CTRL_RST_PCIEA 7
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#define SYS_CTRL_RST_SGDMA 8
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#define SYS_CTRL_RST_CIPHER 9
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#define SYS_CTRL_RST_DDR 10
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#define SYS_CTRL_RST_SATA 11
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#define SYS_CTRL_RST_SATA_LINK 12
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#define SYS_CTRL_RST_SATA_PHY 13
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#define SYS_CTRL_RST_PCIEPHY 14
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#define SYS_CTRL_RST_STATIC 15
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#define SYS_CTRL_RST_GPIO 16
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#define SYS_CTRL_RST_UART1 17
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#define SYS_CTRL_RST_UART2 18
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#define SYS_CTRL_RST_MISC 19
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#define SYS_CTRL_RST_I2S 20
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#define SYS_CTRL_RST_SD 21
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#define SYS_CTRL_RST_MACB 22
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#define SYS_CTRL_RST_PCIEB 23
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#define SYS_CTRL_RST_VIDEO 24
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#define SYS_CTRL_RST_DDR_PHY 25
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#define SYS_CTRL_RST_USBHSPHYB 26
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#define SYS_CTRL_RST_USBDEV 27
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#define SYS_CTRL_RST_ARMDBG 29
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#define SYS_CTRL_RST_PLLA 30
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#define SYS_CTRL_RST_PLLB 31
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#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
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static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
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{
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@ -380,8 +141,9 @@ struct oxnas_pcie {
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void __iomem *cfgbase;
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void __iomem *base;
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void __iomem *inbound;
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void __iomem *outbound;
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void __iomem *pcie_ctrl;
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struct regmap *sys_ctrl;
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unsigned int outbound_offset;
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unsigned int pcie_ctrl_offset;
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int haslink;
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struct platform_device *pdev;
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@ -410,7 +172,7 @@ static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
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static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
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{
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oxnas_register_value_mask(pcie->outbound + PCIE_AHB_SLAVE_CTRL,
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regmap_update_bits(pcie->sys_ctrl, pcie->outbound_offset + PCIE_AHB_SLAVE_CTRL,
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PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
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wmb();
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}
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@ -418,11 +180,13 @@ static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
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static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
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{
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unsigned long end;
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unsigned int val;
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/* Poll for PCIE link up */
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end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
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while (!time_after(jiffies, end)) {
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if (readl(pcie->pcie_ctrl) & PCIE_LINK_UP)
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regmap_read(pcie->sys_ctrl, pcie->pcie_ctrl_offset, &val);
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if (val & PCIE_LINK_UP)
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return 1;
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}
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return 0;
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@ -464,26 +228,27 @@ static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
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*/
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/* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
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writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_IN0_MEM_ADDR);
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writel_relaxed(pcie->non_mem.end, pcie->outbound + PCIE_IN0_MEM_LIMIT);
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writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_POM0_MEM_ADDR);
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regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_ADDR, pcie->non_mem.start);
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regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_LIMIT, pcie->non_mem.end);
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regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM0_MEM_ADDR, pcie->non_mem.start);
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/* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
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writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_IN1_MEM_ADDR);
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writel_relaxed(pcie->pre_mem.end, pcie->outbound + PCIE_IN1_MEM_LIMIT);
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writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_POM1_MEM_ADDR);
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regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_ADDR, pcie->pre_mem.start);
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regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_LIMIT, pcie->pre_mem.end);
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regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM1_MEM_ADDR, pcie->pre_mem.start);
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/* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
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writel_relaxed(pcie->io.start, pcie->outbound + PCIE_IN_IO_ADDR);
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writel_relaxed(pcie->io.end, pcie->outbound + PCIE_IN_IO_LIMIT);
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regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_ADDR, pcie->io.start);
|
||||
regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_LIMIT, pcie->io.end);
|
||||
|
||||
|
||||
/* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
|
||||
writel_relaxed(pcie->cfg.start, pcie->outbound + PCIE_IN_CFG0_ADDR);
|
||||
writel_relaxed(pcie->cfg.end, pcie->outbound + PCIE_IN_CFG0_LIMIT);
|
||||
regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_ADDR, pcie->cfg.start);
|
||||
regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_LIMIT, pcie->cfg.end);
|
||||
wmb();
|
||||
|
||||
/* Enable outbound address translation */
|
||||
oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_OBTRANS);
|
||||
regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, PCIE_OBTRANS, PCIE_OBTRANS);
|
||||
wmb();
|
||||
|
||||
/*
|
||||
@ -640,13 +405,14 @@ static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie
|
||||
}
|
||||
|
||||
void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
|
||||
void __iomem *phybase)
|
||||
void __iomem *phybase,
|
||||
struct regmap *sys_ctrl)
|
||||
{
|
||||
struct reset_control *rstc;
|
||||
int ret;
|
||||
|
||||
/* generate clocks from HCSL buffers, shared parts */
|
||||
writel(HCSL_BIAS_ON|HCSL_PCIE_EN, SYS_CTRL_HCSL_CTRL);
|
||||
regmap_write(sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, HCSL_BIAS_ON|HCSL_PCIE_EN);
|
||||
|
||||
/* Ensure PCIe PHY is properly reset */
|
||||
rstc = reset_control_get(&pdev->dev, "phy");
|
||||
@ -663,7 +429,6 @@ void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
|
||||
}
|
||||
|
||||
/* Enable PCIe Pre-Emphasis: What these value means? */
|
||||
|
||||
writel(ADDR_VAL(0x0014), phybase + PHY_ADDR);
|
||||
writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA);
|
||||
writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA);
|
||||
@ -673,7 +438,7 @@ void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
|
||||
writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA);
|
||||
}
|
||||
|
||||
static int oxnas_pcie_shared_init(struct platform_device *pdev)
|
||||
static int oxnas_pcie_shared_init(struct platform_device *pdev, struct regmap *sys_ctrl)
|
||||
{
|
||||
if (++pcie_shared.refcount == 1) {
|
||||
/* we are the first */
|
||||
@ -683,7 +448,7 @@ static int oxnas_pcie_shared_init(struct platform_device *pdev)
|
||||
--pcie_shared.refcount;
|
||||
return -ENOMEM;
|
||||
}
|
||||
oxnas_pcie_init_shared_hw(pdev, phy);
|
||||
oxnas_pcie_init_shared_hw(pdev, phy, sys_ctrl);
|
||||
iounmap(phy);
|
||||
return 0;
|
||||
} else {
|
||||
@ -730,13 +495,12 @@ oxnas_pcie_map_registers(struct platform_device *pdev,
|
||||
if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
|
||||
&outbound_ctrl_offset))
|
||||
return -EINVAL;
|
||||
/* SYSCRTL is shared by too many drivers, so is mapped by board file */
|
||||
pcie->outbound = IOMEM(OXNAS_SYSCRTL_BASE_VA + outbound_ctrl_offset);
|
||||
pcie->outbound_offset = outbound_ctrl_offset;
|
||||
|
||||
if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
|
||||
&pcie_ctrl_offset))
|
||||
return -EINVAL;
|
||||
pcie->pcie_ctrl = IOMEM(OXNAS_SYSCRTL_BASE_VA + pcie_ctrl_offset);
|
||||
pcie->pcie_ctrl_offset = pcie_ctrl_offset;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -823,7 +587,8 @@ static void oxnas_pcie_init_hw(struct platform_device *pdev,
|
||||
mdelay(100);
|
||||
}
|
||||
|
||||
oxnas_register_set_mask(SYS_CTRL_HCSL_CTRL, BIT(pcie->hcsl_en));
|
||||
regmap_update_bits(pcie->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET,
|
||||
BIT(pcie->hcsl_en), BIT(pcie->hcsl_en));
|
||||
|
||||
/* core */
|
||||
ret = device_reset(&pdev->dev);
|
||||
@ -845,15 +610,17 @@ static void oxnas_pcie_init_hw(struct platform_device *pdev,
|
||||
}
|
||||
|
||||
/* allow entry to L23 state */
|
||||
oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_READY_ENTR_L23);
|
||||
regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
|
||||
PCIE_READY_ENTR_L23, PCIE_READY_ENTR_L23);
|
||||
|
||||
/* Set PCIe core into RootCore mode */
|
||||
oxnas_register_value_mask(pcie->pcie_ctrl, PCIE_DEVICE_TYPE_MASK,
|
||||
PCIE_DEVICE_TYPE_ROOT);
|
||||
regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
|
||||
PCIE_DEVICE_TYPE_MASK, PCIE_DEVICE_TYPE_ROOT);
|
||||
wmb();
|
||||
|
||||
/* Bring up the PCI core */
|
||||
oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_LTSSM);
|
||||
regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
|
||||
PCIE_LTSSM, PCIE_LTSSM);
|
||||
wmb();
|
||||
}
|
||||
|
||||
@ -872,6 +639,10 @@ static int __init oxnas_pcie_probe(struct platform_device *pdev)
|
||||
pcie->haslink = 1;
|
||||
spin_lock_init(&pcie->lock);
|
||||
|
||||
pcie->sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
|
||||
if (IS_ERR(pcie->sys_ctrl))
|
||||
return PTR_ERR(pcie->sys_ctrl);
|
||||
|
||||
ret = oxnas_pcie_init_res(pdev, pcie, np);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -891,7 +662,7 @@ static int __init oxnas_pcie_probe(struct platform_device *pdev)
|
||||
goto err_free_gpio;
|
||||
}
|
||||
|
||||
ret = oxnas_pcie_shared_init(pdev);
|
||||
ret = oxnas_pcie_shared_init(pdev, pcie->sys_ctrl);
|
||||
if (ret)
|
||||
goto err_free_gpio;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user