Cleanup system code and use definitions
SVN-Revision: 6760
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ef53f5db7c
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@ -14,17 +14,12 @@
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/time.h>
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#include <asm/time.h>
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#include <adm5120_info.h>
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#define ADM5120_SOFTRESET 0x12000004
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#define ADM5120_SOFTRESET 0x12000004
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#define STATUS_IE 0x00000001
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#define STATUS_IE 0x00000001
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#define ALLINTS (IE_IRQ0 | IE_IRQ5 | STATUS_IE)
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#define ALLINTS (IE_IRQ0 | IE_IRQ5 | STATUS_IE)
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#define ADM5120_CODEREG 0x12000000
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#define ADM5120_CPU_CLK_MASK 0x00300000
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#define ADM5120_CPU_CLK_175 0x00000000
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#define ADM5120_CPU_CLK_200 0x00100000
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#define ADM5120_CPU_CLK_225 0x00200000
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#define ADM5120_CPU_CLK_250 0x00300000
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void mips_time_init(void);
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void mips_time_init(void);
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extern unsigned int mips_counter_frequency;
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extern unsigned int mips_counter_frequency;
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@ -47,30 +42,9 @@ void adm5120_power_off(void)
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adm5120_halt();
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adm5120_halt();
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}
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}
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void __init mips_time_init(void)
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void __init adm5120_time_init(void)
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{
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{
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u32 clock;
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mips_counter_frequency = adm5120_info.cpu_speed >> 1;
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clock = *(u32*)KSEG1ADDR(ADM5120_CODEREG);
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switch (clock & ADM5120_CPU_CLK_MASK) {
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case ADM5120_CPU_CLK_175:
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mips_counter_frequency = 87500000;
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printk("CPU clock: 175MHz\n");
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break;
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case ADM5120_CPU_CLK_200:
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mips_counter_frequency = 100000000;
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printk("CPU clock: 200MHz\n");
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break;
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case ADM5120_CPU_CLK_225:
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mips_counter_frequency = 112500000;
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printk("CPU clock: 225MHz\n");
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break;
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case ADM5120_CPU_CLK_250:
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mips_counter_frequency = 125000000;
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printk("CPU clock: 250MHz\n");
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break;
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}
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}
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}
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void __init plat_timer_setup(struct irqaction *irq)
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void __init plat_timer_setup(struct irqaction *irq)
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@ -85,7 +59,7 @@ void __init plat_mem_setup(void)
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{
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{
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printk(KERN_INFO "ADM5120 board setup\n");
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printk(KERN_INFO "ADM5120 board setup\n");
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board_time_init = mips_time_init;
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board_time_init = adm5120_time_init;
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//board_timer_setup = mips_timer_setup;
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//board_timer_setup = mips_timer_setup;
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_machine_restart = adm5120_restart;
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_machine_restart = adm5120_restart;
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@ -1,6 +1,8 @@
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/*
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/*
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* Copyright (C) ADMtek Incorporated.
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* Copyright (C) ADMtek Incorporated.
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
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* Copyright (C) 2007 OpenWrt.org
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*/
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*/
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#include <linux/autoconf.h>
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#include <linux/autoconf.h>
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@ -9,11 +11,13 @@
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/init.h>
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volatile u32* pci_config_address_reg = (volatile u32*)KSEG1ADDR(0x115ffff0);
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#include <adm5120_defs.h>
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volatile u32* pci_config_data_reg = (volatile u32*)KSEG1ADDR(0x115ffff8);
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volatile u32* pci_config_address_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR);
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volatile u32* pci_config_data_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA);
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#define PCI_ENABLE 0x80000000
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#define PCI_ENABLE 0x80000000
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *val)
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int size, uint32_t *val)
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{
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{
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@ -1,6 +1,8 @@
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/*
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/*
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* Copyright (C) ADMtek Incorporated.
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* Copyright (C) ADMtek Incorporated.
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
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* Copyright (C) 2007 OpenWrt.org
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*/
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*/
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#include <linux/autoconf.h>
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#include <linux/autoconf.h>
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@ -9,10 +11,10 @@
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/init.h>
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extern struct pci_ops adm5120_pci_ops;
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#include <adm5120_info.h>
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#include <adm5120_defs.h>
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#define ADM5120_CODE 0x12000000
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extern struct pci_ops adm5120_pci_ops;
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#define ADM5120_CODE_PQFP 0x20000000
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#define PCI_CMM_IOACC_EN 0x1
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#define PCI_CMM_IOACC_EN 0x1
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#define PCI_CMM_MEMACC_EN 0x2
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#define PCI_CMM_MEMACC_EN 0x2
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@ -24,16 +26,16 @@ extern struct pci_ops adm5120_pci_ops;
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struct resource pci_io_resource = {
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struct resource pci_io_resource = {
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.name = "PCI IO space",
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.name = "ADM5120 PCI I/O",
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.start = 0x11500000,
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.start = ADM5120_PCIIO_BASE,
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.end = 0x115ffff0-1,
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.end = ADM5120_PCICFG_ADDR-1,
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.flags = IORESOURCE_IO
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.flags = IORESOURCE_IO
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};
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};
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struct resource pci_mem_resource = {
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struct resource pci_mem_resource = {
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.name = "PCI memory space",
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.name = "ADM5120 PCI MEM",
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.start = 0x11400000,
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.start = ADM5120_PCIMEM_BASE,
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.end = 0x11500000,
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.end = ADM5120_PCIIO_BASE-1,
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.flags = IORESOURCE_MEM
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.flags = IORESOURCE_MEM
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};
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};
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@ -71,12 +73,13 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
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static int __init adm5120_pci_setup(void)
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static int __init adm5120_pci_setup(void)
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{
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{
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int pci_bios;
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if ((*(volatile u32 *)(KSEG1ADDR(ADM5120_CODE))) & ADM5120_CODE_PQFP) {
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pci_bios = adm5120_has_pci();
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printk("System has no PCI BIOS (ADM5120 PQFP)\n");
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printk("adm5120: system has %sPCI BIOS\n", pci_bios ? "" : "no ");
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if (pci_bios == 0)
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return 1;
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return 1;
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}
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printk("System has PCI BIOS (ADM5120 BGA)\n");
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/* Avoid ISA compat ranges. */
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/* Avoid ISA compat ranges. */
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PCIBIOS_MIN_IO = 0x00000000;
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PCIBIOS_MIN_IO = 0x00000000;
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@ -84,7 +87,7 @@ static int __init adm5120_pci_setup(void)
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/* Set I/O resource limits. */
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/* Set I/O resource limits. */
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ioport_resource.end = 0x1fffffff;
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ioport_resource.end = 0x1fffffff;
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iomem_resource.end = 0xffffffff;
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iomem_resource.end = 0xffffffff;
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register_pci_controller(&adm5120_controller);
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register_pci_controller(&adm5120_controller);
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return 0;
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return 0;
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