kernel: Add GigaDevice GD5F4GQ4xC SPI NAND flash
This flash was found on the Imagination Technologies Creator Ci40 (Marduk). Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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Hauke Mehrtens
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@ -0,0 +1,39 @@
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From 5f312dcb38b8003d9711290366cd4b1def5daf3b Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 16 Aug 2020 14:43:35 +0200
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Subject: [PATCH v2 445/447] mtd: spinand: gigadevice: Only one dummy byte in
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QUADIO
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The datasheet only lists one dummy byte in the 0xEH operation for the
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following chips:
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* GD5F1GQ4xExxG
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* GD5F1GQ4xFxxG
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* GD5F1GQ4UAYIG
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* GD5F4GQ4UAYIG
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Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/mtd/nand/spi/gigadevice.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -21,7 +21,7 @@
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#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4)
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static SPINAND_OP_VARIANTS(read_cache_variants,
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- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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@@ -29,7 +29,7 @@ static SPINAND_OP_VARIANTS(read_cache_va
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(read_cache_variants_f,
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- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
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@ -0,0 +1,67 @@
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From f72e99ada020a81e3e4ef79c0a83ede7e9d6c7b1 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 16 Aug 2020 14:42:17 +0200
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Subject: [PATCH v2 446/447] mtd: spinand: gigadevice: Add QE Bit
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The following GigaDevice chips have the QE BIT in the feature flags, I
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checked the datasheets, but did not try this.
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* GD5F1GQ4xExxG
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* GD5F1GQ4xFxxG
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* GD5F1GQ4UAYIG
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* GD5F4GQ4UAYIG
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The Quad operations like 0xEB mention that the QE bit has to be set.
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Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/mtd/nand/spi/gigadevice.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -201,7 +201,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F2GQ4xA", 0xF2,
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@@ -210,7 +210,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F4GQ4xA", 0xF4,
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@@ -219,7 +219,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
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@@ -228,7 +228,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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gd5fxgq4uexxg_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148,
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@@ -237,7 +237,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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gd5fxgq4ufxxg_ecc_get_status)),
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};
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@ -0,0 +1,87 @@
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From 30521ccfb4597f91b9e5c7967acef9c7c85e58a8 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Wed, 12 Aug 2020 22:50:26 +0200
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Subject: [PATCH v2 447/447] mtd: spinand: gigadevice: Add support for
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GD5F4GQ4xC
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This adds support for the following 4GiB chips:
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GD5F4GQ4RCYIG 1.8V
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GD5F4GQ4UCYIG 3.3V
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The datasheet can be found here:
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https://www.novitronic.ch/sixcms/media.php/2/DS-00173-GD5F4GQ4xCxIG-Rev1.574695.pdf
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The GD5F4GQ4UCYIGT (3.3V) version is used on the Imagination
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Technologies Creator Ci40 (Marduk), the 1.8V version was not tested.
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This device only works in single SPI mode and not in dual or quad mode
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for me on this board.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/mtd/nand/spi/gigadevice.c | 49 +++++++++++++++++++++++++++++++
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1 file changed, 49 insertions(+)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -132,6 +132,35 @@ static const struct mtd_ooblayout_ops gd
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.free = gd5fxgq4_variant2_ooblayout_free,
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};
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+static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *oobregion)
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+{
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+ if (section)
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+ return -ERANGE;
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+
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+ oobregion->offset = 128;
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+ oobregion->length = 128;
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+
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+ return 0;
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+}
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+
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+static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *oobregion)
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+{
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+ if (section)
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+ return -ERANGE;
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+
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+ oobregion->offset = 1;
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+ oobregion->length = 127;
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+
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+ return 0;
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+}
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+
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+static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = {
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+ .ecc = gd5fxgq4xc_ooblayout_256_ecc,
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+ .free = gd5fxgq4xc_ooblayout_256_free,
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+};
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+
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static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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@@ -222,6 +251,24 @@ static const struct spinand_info gigadev
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GQ4RC", 0xa468,
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+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
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+ gd5fxgq4ufxxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GQ4UC", 0xb468,
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+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
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+ gd5fxgq4ufxxg_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
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NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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