add 64 bit dma support to broadcom-wl, fixes wrt300n wifi support
SVN-Revision: 5717
This commit is contained in:
Felix Fietkau
parent
1c12036f6d
commit
aae28d7120
@ -11,7 +11,7 @@
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#
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# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
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EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
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EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER=1 -DBCMDMA64=1
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O_TARGET := wl$(MOD_NAME).o
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@ -94,6 +94,14 @@ typedef struct dma_info {
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uint dataoffsethigh; /* high 32 bits */
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} dma_info_t;
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#ifdef BCMDMA64
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#define DMA64_ENAB(di) ((di)->dma64)
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#define DMA64_CAP TRUE
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#else
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#define DMA64_ENAB(di) (0)
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#define DMA64_CAP FALSE
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#endif
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/* descriptor bumping macros */
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#define XXD(x, n) ((x) & ((n) - 1)) /* faster than %, but n must be power of 2 */
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#define TXD(x) XXD((x), di->ntxd)
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@ -114,7 +122,7 @@ typedef struct dma_info {
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/* common prototypes */
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static bool _dma_isaddrext(dma_info_t *di);
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static bool dma32_alloc(dma_info_t *di, uint direction);
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static bool _dma_alloc(dma_info_t *di, uint direction);
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static void _dma_detach(dma_info_t *di);
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static void _dma_ddtable_init(dma_info_t *di, uint direction, ulong pa);
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static void _dma_rxinit(dma_info_t *di);
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@ -129,7 +137,7 @@ static void _dma_txunblock(dma_info_t *di);
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static uint _dma_txactive(dma_info_t *di);
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static void* _dma_peeknexttxp(dma_info_t *di);
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static uintptr _dma_getvar(dma_info_t *di, char *name);
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static uintptr _dma_getvar(dma_info_t *di, const char *name);
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static void _dma_counterreset(dma_info_t *di);
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static void _dma_fifoloopbackenable(dma_info_t *di);
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@ -154,6 +162,94 @@ static bool dma32_rxstopped(dma_info_t *di);
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static bool dma32_rxenabled(dma_info_t *di);
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static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs);
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/* ** 64 bit DMA prototypes and stubs */
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#ifdef BCMDMA64
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static bool dma64_alloc(dma_info_t *di, uint direction);
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static bool dma64_txreset(dma_info_t *di);
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static bool dma64_rxreset(dma_info_t *di);
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static bool dma64_txsuspendedidle(dma_info_t *di);
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static int dma64_txfast(dma_info_t *di, void *p0, bool commit);
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static void *dma64_getnexttxp(dma_info_t *di, bool forceall);
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static void *dma64_getnextrxp(dma_info_t *di, bool forceall);
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static void dma64_txrotate(dma_info_t *di);
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static bool dma64_rxidle(dma_info_t *di);
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static void dma64_txinit(dma_info_t *di);
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static bool dma64_txenabled(dma_info_t *di);
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static void dma64_txsuspend(dma_info_t *di);
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static void dma64_txresume(dma_info_t *di);
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static bool dma64_txsuspended(dma_info_t *di);
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static void dma64_txreclaim(dma_info_t *di, bool forceall);
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static bool dma64_txstopped(dma_info_t *di);
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static bool dma64_rxstopped(dma_info_t *di);
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static bool dma64_rxenabled(dma_info_t *di);
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static bool _dma64_addrext(osl_t *osh, dma64regs_t *dma64regs);
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#else
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static bool dma64_alloc(dma_info_t *di, uint direction) { return FALSE; }
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static bool dma64_txreset(dma_info_t *di) { return FALSE; }
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static bool dma64_rxreset(dma_info_t *di) { return FALSE; }
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static bool dma64_txsuspendedidle(dma_info_t *di) { return FALSE;}
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static int dma64_txfast(dma_info_t *di, void *p0, bool commit) { return 0; }
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static void *dma64_getnexttxp(dma_info_t *di, bool forceall) { return NULL; }
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static void *dma64_getnextrxp(dma_info_t *di, bool forceall) { return NULL; }
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static void dma64_txrotate(dma_info_t *di) { return; }
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static bool dma64_rxidle(dma_info_t *di) { return FALSE; }
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static void dma64_txinit(dma_info_t *di) { return; }
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static bool dma64_txenabled(dma_info_t *di) { return FALSE; }
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static void dma64_txsuspend(dma_info_t *di) { return; }
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static void dma64_txresume(dma_info_t *di) { return; }
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static bool dma64_txsuspended(dma_info_t *di) {return FALSE; }
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static void dma64_txreclaim(dma_info_t *di, bool forceall) { return; }
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static bool dma64_txstopped(dma_info_t *di) { return FALSE; }
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static bool dma64_rxstopped(dma_info_t *di) { return FALSE; }
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static bool dma64_rxenabled(dma_info_t *di) { return FALSE; }
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static bool _dma64_addrext(osl_t *osh, dma64regs_t *dma64regs) { return FALSE; }
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#endif /* BCMDMA64 */
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static di_fcn_t dma64proc = {
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(di_detach_t)_dma_detach,
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(di_txinit_t)dma64_txinit,
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(di_txreset_t)dma64_txreset,
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(di_txenabled_t)dma64_txenabled,
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(di_txsuspend_t)dma64_txsuspend,
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(di_txresume_t)dma64_txresume,
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(di_txsuspended_t)dma64_txsuspended,
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(di_txsuspendedidle_t)dma64_txsuspendedidle,
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(di_txfast_t)dma64_txfast,
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(di_txstopped_t)dma64_txstopped,
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(di_txreclaim_t)dma64_txreclaim,
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(di_getnexttxp_t)dma64_getnexttxp,
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(di_peeknexttxp_t)_dma_peeknexttxp,
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(di_txblock_t)_dma_txblock,
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(di_txunblock_t)_dma_txunblock,
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(di_txactive_t)_dma_txactive,
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(di_txrotate_t)dma64_txrotate,
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(di_rxinit_t)_dma_rxinit,
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(di_rxreset_t)dma64_rxreset,
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(di_rxidle_t)dma64_rxidle,
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(di_rxstopped_t)dma64_rxstopped,
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(di_rxenable_t)_dma_rxenable,
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(di_rxenabled_t)dma64_rxenabled,
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(di_rx_t)_dma_rx,
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(di_rxfill_t)_dma_rxfill,
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(di_rxreclaim_t)_dma_rxreclaim,
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(di_getnextrxp_t)_dma_getnextrxp,
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(di_fifoloopbackenable_t)_dma_fifoloopbackenable,
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(di_getvar_t)_dma_getvar,
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(di_counterreset_t)_dma_counterreset,
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NULL,
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NULL,
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NULL,
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34
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};
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static di_fcn_t dma32proc = {
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(di_detach_t)_dma_detach,
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@ -213,6 +309,16 @@ dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
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/* old chips w/o sb is no longer supported */
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ASSERT(sbh != NULL);
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di->dma64 = ((sb_coreflagshi(sbh, 0, 0) & SBTMH_DMA64) == SBTMH_DMA64);
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#ifndef BCMDMA64
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if (di->dma64) {
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DMA_ERROR(("dma_attach: driver doesn't have the capability to support "
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"64 bits DMA\n"));
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goto fail;
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}
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#endif
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/* check arguments */
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ASSERT(ISPOWEROF2(ntxd));
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ASSERT(ISPOWEROF2(nrxd));
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@ -223,14 +329,27 @@ dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
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/* init dma reg pointer */
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if (di->dma64) {
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ASSERT(ntxd <= D64MAXDD);
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ASSERT(nrxd <= D64MAXDD);
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di->d64txregs = (dma64regs_t *)dmaregstx;
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di->d64rxregs = (dma64regs_t *)dmaregsrx;
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di->dma64align = D64RINGALIGN;
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if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
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/* for smaller dd table, HW relax the alignment requirement */
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di->dma64align = D64RINGALIGN / 2;
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}
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} else {
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ASSERT(ntxd <= D32MAXDD);
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ASSERT(nrxd <= D32MAXDD);
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di->d32txregs = (dma32regs_t *)dmaregstx;
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di->d32rxregs = (dma32regs_t *)dmaregsrx;
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}
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DMA_TRACE(("%s: dma_attach: %s osh %p ntxd %d nrxd %d rxbufsize %d nrxpost %d "
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"rxoffset %d dmaregstx %p dmaregsrx %p\n",
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name, "DMA32", osh, ntxd, nrxd, rxbufsize,
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name, (di->dma64 ? "DMA64" : "DMA32"), osh, ntxd, nrxd, rxbufsize,
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nrxpost, rxoffset, dmaregstx, dmaregsrx));
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/* make a private copy of our callers name */
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@ -265,8 +384,15 @@ dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
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di->dataoffsetlow = 0;
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/* for pci bus, add offset */
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if (sbh->bustype == PCI_BUS) {
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if ((sbh->buscoretype == SB_PCIE) && di->dma64) {
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/* pcie with DMA64 */
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di->ddoffsetlow = 0;
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di->ddoffsethigh = SB_PCIE_DMA_H32;
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} else {
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/* pci(DMA32/DMA64) or pcie with DMA32 */
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di->ddoffsetlow = SB_PCI_DMA;
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di->ddoffsethigh = 0;
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}
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di->dataoffsetlow = di->ddoffsetlow;
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di->dataoffsethigh = di->ddoffsethigh;
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}
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@ -301,13 +427,13 @@ dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
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/* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
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if (ntxd) {
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if (!dma32_alloc(di, DMA_TX))
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if (!_dma_alloc(di, DMA_TX))
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goto fail;
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}
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/* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
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if (nrxd) {
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if (!dma32_alloc(di, DMA_RX))
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if (!_dma_alloc(di, DMA_RX))
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goto fail;
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}
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@ -348,7 +474,7 @@ dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
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di->rxp_dmah = NULL;
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/* initialize opsvec of function pointers */
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di->hnddma.di_fn = dma32proc;
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di->hnddma.di_fn = DMA64_ENAB(di) ? dma64proc : dma32proc;
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return ((hnddma_t *)di);
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@ -381,6 +507,34 @@ dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, ulong pa, uint outidx, uint32 *f
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}
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}
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static INLINE void
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dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, ulong pa, uint outidx, uint32 *flags,
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uint32 bufcount)
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{
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uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
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/* PCI bus with big(>1G) physical address, use address extension */
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if ((di->dataoffsetlow != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
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W_SM(&ddring[outidx].addrlow, BUS_SWAP32(pa + di->dataoffsetlow));
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W_SM(&ddring[outidx].addrhigh, BUS_SWAP32(0 + di->dataoffsethigh));
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W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
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W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
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} else {
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/* address extension */
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uint32 ae;
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ASSERT(di->addrext);
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ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
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pa &= ~PCI32ADDR_HIGH;
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ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE;
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W_SM(&ddring[outidx].addrlow, BUS_SWAP32(pa + di->dataoffsetlow));
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W_SM(&ddring[outidx].addrhigh, BUS_SWAP32(0 + di->dataoffsethigh));
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W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
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W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
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}
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}
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static bool
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_dma32_addrext(osl_t *osh, dma32regs_t *dma32regs)
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{
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@ -392,6 +546,16 @@ _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs)
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return ((w & XC_AE) == XC_AE);
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}
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static bool
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_dma_alloc(dma_info_t *di, uint direction)
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{
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if (DMA64_ENAB(di)) {
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return dma64_alloc(di, direction);
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} else {
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return dma32_alloc(di, direction);
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}
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}
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/* !! may be called with core in reset */
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static void
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_dma_detach(dma_info_t *di)
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@ -406,12 +570,21 @@ _dma_detach(dma_info_t *di)
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ASSERT(di->rxin == di->rxout);
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/* free dma descriptor rings */
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if (DMA64_ENAB(di)) {
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if (di->txd64)
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DMA_FREE_CONSISTENT(di->osh, ((int8*)(uintptr)di->txd64 - di->txdalign),
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di->txdalloc, (di->txdpa - di->txdalign), &di->tx_dmah);
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if (di->rxd64)
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DMA_FREE_CONSISTENT(di->osh, ((int8*)(uintptr)di->rxd64 - di->rxdalign),
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di->rxdalloc, (di->rxdpa - di->rxdalign), &di->rx_dmah);
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} else {
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if (di->txd32)
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DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd32 - di->txdalign),
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DMA_FREE_CONSISTENT(di->osh, ((int8*)(uintptr)di->txd32 - di->txdalign),
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di->txdalloc, (di->txdpa - di->txdalign), &di->tx_dmah);
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if (di->rxd32)
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DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd32 - di->rxdalign),
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DMA_FREE_CONSISTENT(di->osh, ((int8*)(uintptr)di->rxd32 - di->rxdalign),
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di->rxdalloc, (di->rxdpa - di->rxdalign), &di->rx_dmah);
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}
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/* free packet pointer vectors */
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if (di->txp)
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@ -436,7 +609,27 @@ _dma_detach(dma_info_t *di)
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static bool
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_dma_isaddrext(dma_info_t *di)
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{
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if (di->d32txregs)
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if (DMA64_ENAB(di)) {
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/* DMA64 supports full 32 bits or 64 bits. AE is always valid */
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/* not all tx or rx channel are available */
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if (di->d64txregs != NULL) {
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if (!_dma64_addrext(di->osh, di->d64txregs)) {
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have AE set\n",
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di->name));
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ASSERT(0);
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}
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return TRUE;
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} else if (di->d64rxregs != NULL) {
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if (!_dma64_addrext(di->osh, di->d64rxregs)) {
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have AE set\n",
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di->name));
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ASSERT(0);
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}
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return TRUE;
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}
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return FALSE;
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} else if (di->d32txregs)
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return (_dma32_addrext(di->osh, di->d32txregs));
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else if (di->d32rxregs)
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return (_dma32_addrext(di->osh, di->d32rxregs));
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@ -447,6 +640,39 @@ _dma_isaddrext(dma_info_t *di)
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static void
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_dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
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{
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if (DMA64_ENAB(di)) {
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if ((di->ddoffsetlow != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
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if (direction == DMA_TX) {
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W_REG(di->osh, &di->d64txregs->addrlow, (pa + di->ddoffsetlow));
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W_REG(di->osh, &di->d64txregs->addrhigh, di->ddoffsethigh);
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} else {
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W_REG(di->osh, &di->d64rxregs->addrlow, (pa + di->ddoffsetlow));
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W_REG(di->osh, &di->d64rxregs->addrhigh, di->ddoffsethigh);
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}
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} else {
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/* DMA64 32bits address extension */
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uint32 ae;
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ASSERT(di->addrext);
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/* shift the high bit(s) from pa to ae */
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ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
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pa &= ~PCI32ADDR_HIGH;
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if (direction == DMA_TX) {
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W_REG(di->osh, &di->d64txregs->addrlow, (pa + di->ddoffsetlow));
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W_REG(di->osh, &di->d64txregs->addrhigh, di->ddoffsethigh);
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SET_REG(di->osh, &di->d64txregs->control, D64_XC_AE,
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(ae << D64_XC_AE_SHIFT));
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} else {
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W_REG(di->osh, &di->d64rxregs->addrlow, (pa + di->ddoffsetlow));
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W_REG(di->osh, &di->d64rxregs->addrhigh, di->ddoffsethigh);
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SET_REG(di->osh, &di->d64rxregs->control, D64_RC_AE,
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(ae << D64_RC_AE_SHIFT));
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}
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}
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} else {
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if ((di->ddoffsetlow != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
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if (direction == DMA_TX)
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W_REG(di->osh, &di->d32txregs->addr, (pa + di->ddoffsetlow));
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@ -469,12 +695,16 @@ _dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
|
||||
SET_REG(di->osh, &di->d32rxregs->control, RC_AE, ae <<RC_AE_SHIFT);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
_dma_fifoloopbackenable(dma_info_t *di)
|
||||
{
|
||||
DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
|
||||
if (DMA64_ENAB(di))
|
||||
OR_REG(di->osh, &di->d64txregs->control, D64_XC_LE);
|
||||
else
|
||||
OR_REG(di->osh, &di->d32txregs->control, XC_LE);
|
||||
}
|
||||
|
||||
@ -489,9 +719,15 @@ _dma_rxinit(dma_info_t *di)
|
||||
di->rxin = di->rxout = 0;
|
||||
|
||||
/* clear rx descriptor ring */
|
||||
BZERO_SM((void *)di->rxd32, (di->nrxd * sizeof(dma32dd_t)));
|
||||
if (DMA64_ENAB(di)) {
|
||||
BZERO_SM((void *)(uintptr)di->rxd64, (di->nrxd * sizeof(dma64dd_t)));
|
||||
_dma_rxenable(di);
|
||||
_dma_ddtable_init(di, DMA_RX, di->rxdpa);
|
||||
} else {
|
||||
BZERO_SM((void *)(uintptr)di->rxd32, (di->nrxd * sizeof(dma32dd_t)));
|
||||
_dma_rxenable(di);
|
||||
_dma_ddtable_init(di, DMA_RX, di->rxdpa);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
@ -499,6 +735,10 @@ _dma_rxenable(dma_info_t *di)
|
||||
{
|
||||
DMA_TRACE(("%s: dma_rxenable\n", di->name));
|
||||
|
||||
if (DMA64_ENAB(di))
|
||||
W_REG(di->osh, &di->d64rxregs->control,
|
||||
((di->rxoffset << D64_RC_RO_SHIFT) | D64_RC_RE));
|
||||
else
|
||||
W_REG(di->osh, &di->d32rxregs->control, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
|
||||
}
|
||||
|
||||
@ -602,16 +842,28 @@ _dma_rxfill(dma_info_t *di)
|
||||
|
||||
/* reset flags for each descriptor */
|
||||
flags = 0;
|
||||
if (DMA64_ENAB(di)) {
|
||||
if (rxout == (di->nrxd - 1))
|
||||
flags = D64_CTRL1_EOT;
|
||||
|
||||
dma64_dd_upd(di, di->rxd64, pa, rxout, &flags, di->rxbufsize);
|
||||
} else {
|
||||
if (rxout == (di->nrxd - 1))
|
||||
flags = CTRL_EOT;
|
||||
|
||||
dma32_dd_upd(di, di->rxd32, pa, rxout, &flags, di->rxbufsize);
|
||||
}
|
||||
rxout = NEXTRXD(rxout);
|
||||
}
|
||||
|
||||
di->rxout = rxout;
|
||||
|
||||
/* update the chip lastdscr pointer */
|
||||
if (DMA64_ENAB(di)) {
|
||||
W_REG(di->osh, &di->d64rxregs->ptr, I2B(rxout, dma64dd_t));
|
||||
} else {
|
||||
W_REG(di->osh, &di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
|
||||
}
|
||||
}
|
||||
|
||||
/* like getnexttxp but no reclaim */
|
||||
@ -623,7 +875,11 @@ _dma_peeknexttxp(dma_info_t *di)
|
||||
if (di->ntxd == 0)
|
||||
return (NULL);
|
||||
|
||||
if (DMA64_ENAB(di)) {
|
||||
end = B2I(R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
|
||||
} else {
|
||||
end = B2I(R_REG(di->osh, &di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
|
||||
}
|
||||
|
||||
for (i = di->txin; i != end; i = NEXTTXD(i))
|
||||
if (di->txp[i])
|
||||
@ -654,7 +910,11 @@ _dma_getnextrxp(dma_info_t *di, bool forceall)
|
||||
if (di->nrxd == 0)
|
||||
return (NULL);
|
||||
|
||||
if (DMA64_ENAB(di)) {
|
||||
return dma64_getnextrxp(di, forceall);
|
||||
} else {
|
||||
return dma32_getnextrxp(di, forceall);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
@ -686,7 +946,7 @@ _dma_counterreset(dma_info_t *di)
|
||||
|
||||
/* get the address of the var in order to change later */
|
||||
static uintptr
|
||||
_dma_getvar(dma_info_t *di, char *name)
|
||||
_dma_getvar(dma_info_t *di, const char *name)
|
||||
{
|
||||
if (!strcmp(name, "&txavail"))
|
||||
return ((uintptr) &(di->hnddma.txavail));
|
||||
@ -717,7 +977,7 @@ dma32_txinit(dma_info_t *di)
|
||||
di->hnddma.txavail = di->ntxd - 1;
|
||||
|
||||
/* clear tx descriptor ring */
|
||||
BZERO_SM((void *)di->txd32, (di->ntxd * sizeof(dma32dd_t)));
|
||||
BZERO_SM((void *)(uintptr)di->txd32, (di->ntxd * sizeof(dma32dd_t)));
|
||||
W_REG(di->osh, &di->d32txregs->control, XC_XE);
|
||||
_dma_ddtable_init(di, DMA_TX, di->txdpa);
|
||||
}
|
||||
@ -806,7 +1066,7 @@ dma32_alloc(dma_info_t *di, uint direction)
|
||||
}
|
||||
|
||||
di->txd32 = (dma32dd_t *) ROUNDUP((uintptr)va, D32RINGALIGN);
|
||||
di->txdalign = (uint)((int8*)di->txd32 - (int8*)va);
|
||||
di->txdalign = (uint)((int8*)(uintptr)di->txd32 - (int8*)va);
|
||||
di->txdpa += di->txdalign;
|
||||
di->txdalloc = size;
|
||||
ASSERT(ISALIGNED((uintptr)di->txd32, D32RINGALIGN));
|
||||
@ -817,7 +1077,7 @@ dma32_alloc(dma_info_t *di, uint direction)
|
||||
return FALSE;
|
||||
}
|
||||
di->rxd32 = (dma32dd_t *) ROUNDUP((uintptr)va, D32RINGALIGN);
|
||||
di->rxdalign = (uint)((int8*)di->rxd32 - (int8*)va);
|
||||
di->rxdalign = (uint)((int8*)(uintptr)di->rxd32 - (int8*)va);
|
||||
di->rxdpa += di->rxdalign;
|
||||
di->rxdalloc = size;
|
||||
ASSERT(ISALIGNED((uintptr)di->rxd32, D32RINGALIGN));
|
||||
@ -1134,6 +1394,461 @@ dma32_txrotate(dma_info_t *di)
|
||||
W_REG(di->osh, &di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
|
||||
}
|
||||
|
||||
/* 64 bits DMA functions */
|
||||
|
||||
#ifdef BCMDMA64
|
||||
static void
|
||||
dma64_txinit(dma_info_t *di)
|
||||
{
|
||||
DMA_TRACE(("%s: dma_txinit\n", di->name));
|
||||
|
||||
if (di->ntxd == 0)
|
||||
return;
|
||||
|
||||
di->txin = di->txout = 0;
|
||||
di->hnddma.txavail = di->ntxd - 1;
|
||||
|
||||
/* clear tx descriptor ring */
|
||||
BZERO_SM((void *)(uintptr)di->txd64, (di->ntxd * sizeof(dma64dd_t)));
|
||||
W_REG(di->osh, &di->d64txregs->control, D64_XC_XE);
|
||||
_dma_ddtable_init(di, DMA_TX, di->txdpa);
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_txenabled(dma_info_t *di)
|
||||
{
|
||||
uint32 xc;
|
||||
|
||||
/* If the chip is dead, it is not enabled :-) */
|
||||
xc = R_REG(di->osh, &di->d64txregs->control);
|
||||
return ((xc != 0xffffffff) && (xc & D64_XC_XE));
|
||||
}
|
||||
|
||||
static void
|
||||
dma64_txsuspend(dma_info_t *di)
|
||||
{
|
||||
DMA_TRACE(("%s: dma_txsuspend\n", di->name));
|
||||
|
||||
if (di->ntxd == 0)
|
||||
return;
|
||||
|
||||
OR_REG(di->osh, &di->d64txregs->control, D64_XC_SE);
|
||||
}
|
||||
|
||||
static void
|
||||
dma64_txresume(dma_info_t *di)
|
||||
{
|
||||
DMA_TRACE(("%s: dma_txresume\n", di->name));
|
||||
|
||||
if (di->ntxd == 0)
|
||||
return;
|
||||
|
||||
AND_REG(di->osh, &di->d64txregs->control, ~D64_XC_SE);
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_txsuspended(dma_info_t *di)
|
||||
{
|
||||
return (di->ntxd == 0) || ((R_REG(di->osh, &di->d64txregs->control) & D64_XC_SE)
|
||||
== D64_XC_SE);
|
||||
}
|
||||
|
||||
static void
|
||||
dma64_txreclaim(dma_info_t *di, bool forceall)
|
||||
{
|
||||
void *p;
|
||||
|
||||
DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
|
||||
|
||||
while ((p = dma64_getnexttxp(di, forceall)))
|
||||
PKTFREE(di->osh, p, TRUE);
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_txstopped(dma_info_t *di)
|
||||
{
|
||||
return ((R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_STOPPED);
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_rxstopped(dma_info_t *di)
|
||||
{
|
||||
return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK) == D64_RS0_RS_STOPPED);
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_alloc(dma_info_t *di, uint direction)
|
||||
{
|
||||
uint size;
|
||||
uint ddlen;
|
||||
uint32 alignbytes;
|
||||
void *va;
|
||||
|
||||
ddlen = sizeof(dma64dd_t);
|
||||
|
||||
size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
|
||||
|
||||
alignbytes = di->dma64align;
|
||||
|
||||
if (!ISALIGNED(DMA_CONSISTENT_ALIGN, alignbytes))
|
||||
size += alignbytes;
|
||||
|
||||
if (direction == DMA_TX) {
|
||||
if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa, &di->tx_dmah)) == NULL) {
|
||||
DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n",
|
||||
di->name));
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
di->txd64 = (dma64dd_t *) ROUNDUP((uintptr)va, alignbytes);
|
||||
di->txdalign = (uint)((int8*)(uintptr)di->txd64 - (int8*)va);
|
||||
di->txdpa += di->txdalign;
|
||||
di->txdalloc = size;
|
||||
ASSERT(ISALIGNED((uintptr)di->txd64, alignbytes));
|
||||
} else {
|
||||
if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa, &di->rx_dmah)) == NULL) {
|
||||
DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n",
|
||||
di->name));
|
||||
return FALSE;
|
||||
}
|
||||
di->rxd64 = (dma64dd_t *) ROUNDUP((uintptr)va, alignbytes);
|
||||
di->rxdalign = (uint)((int8*)(uintptr)di->rxd64 - (int8*)va);
|
||||
di->rxdpa += di->rxdalign;
|
||||
di->rxdalloc = size;
|
||||
ASSERT(ISALIGNED((uintptr)di->rxd64, alignbytes));
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_txreset(dma_info_t *di)
|
||||
{
|
||||
uint32 status;
|
||||
|
||||
if (di->ntxd == 0)
|
||||
return TRUE;
|
||||
|
||||
/* suspend tx DMA first */
|
||||
W_REG(di->osh, &di->d64txregs->control, D64_XC_SE);
|
||||
SPINWAIT(((status = (R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK)) !=
|
||||
D64_XS0_XS_DISABLED) &&
|
||||
(status != D64_XS0_XS_IDLE) &&
|
||||
(status != D64_XS0_XS_STOPPED),
|
||||
10000);
|
||||
|
||||
W_REG(di->osh, &di->d64txregs->control, 0);
|
||||
SPINWAIT(((status = (R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK)) !=
|
||||
D64_XS0_XS_DISABLED),
|
||||
10000);
|
||||
|
||||
/* wait for the last transaction to complete */
|
||||
OSL_DELAY(300);
|
||||
|
||||
return (status == D64_XS0_XS_DISABLED);
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_rxidle(dma_info_t *di)
|
||||
{
|
||||
DMA_TRACE(("%s: dma_rxidle\n", di->name));
|
||||
|
||||
if (di->nrxd == 0)
|
||||
return TRUE;
|
||||
|
||||
return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
|
||||
R_REG(di->osh, &di->d64rxregs->ptr));
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_rxreset(dma_info_t *di)
|
||||
{
|
||||
uint32 status;
|
||||
|
||||
if (di->nrxd == 0)
|
||||
return TRUE;
|
||||
|
||||
W_REG(di->osh, &di->d64rxregs->control, 0);
|
||||
SPINWAIT(((status = (R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK)) !=
|
||||
D64_RS0_RS_DISABLED),
|
||||
10000);
|
||||
|
||||
return (status == D64_RS0_RS_DISABLED);
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_rxenabled(dma_info_t *di)
|
||||
{
|
||||
uint32 rc;
|
||||
|
||||
rc = R_REG(di->osh, &di->d64rxregs->control);
|
||||
return ((rc != 0xffffffff) && (rc & D64_RC_RE));
|
||||
}
|
||||
|
||||
static bool
|
||||
dma64_txsuspendedidle(dma_info_t *di)
|
||||
{
|
||||
|
||||
if (di->ntxd == 0)
|
||||
return TRUE;
|
||||
|
||||
if (!(R_REG(di->osh, &di->d64txregs->control) & D64_XC_SE))
|
||||
return 0;
|
||||
|
||||
if ((R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_IDLE)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* !! tx entry routine */
|
||||
static int
|
||||
dma64_txfast(dma_info_t *di, void *p0, bool commit)
|
||||
{
|
||||
void *p, *next;
|
||||
uchar *data;
|
||||
uint len;
|
||||
uint txout;
|
||||
uint32 flags = 0;
|
||||
uint32 pa;
|
||||
|
||||
DMA_TRACE(("%s: dma_txfast\n", di->name));
|
||||
|
||||
txout = di->txout;
|
||||
|
||||
/*
|
||||
* Walk the chain of packet buffers
|
||||
* allocating and initializing transmit descriptor entries.
|
||||
*/
|
||||
for (p = p0; p; p = next) {
|
||||
data = PKTDATA(di->osh, p);
|
||||
len = PKTLEN(di->osh, p);
|
||||
next = PKTNEXT(di->osh, p);
|
||||
|
||||
/* return nonzero if out of tx descriptors */
|
||||
if (NEXTTXD(txout) == di->txin)
|
||||
goto outoftxd;
|
||||
|
||||
if (len == 0)
|
||||
continue;
|
||||
|
||||
/* get physical address of buffer start */
|
||||
pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
|
||||
|
||||
flags = 0;
|
||||
if (p == p0)
|
||||
flags |= D64_CTRL1_SOF;
|
||||
if (next == NULL)
|
||||
flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
|
||||
if (txout == (di->ntxd - 1))
|
||||
flags |= D64_CTRL1_EOT;
|
||||
|
||||
dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
|
||||
ASSERT(di->txp[txout] == NULL);
|
||||
|
||||
txout = NEXTTXD(txout);
|
||||
}
|
||||
|
||||
/* if last txd eof not set, fix it */
|
||||
if (!(flags & D64_CTRL1_EOF))
|
||||
W_SM(&di->txd64[PREVTXD(txout)].ctrl1,
|
||||
BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
|
||||
|
||||
/* save the packet */
|
||||
di->txp[PREVTXD(txout)] = p0;
|
||||
|
||||
/* bump the tx descriptor index */
|
||||
di->txout = txout;
|
||||
|
||||
/* kick the chip */
|
||||
if (commit)
|
||||
W_REG(di->osh, &di->d64txregs->ptr, I2B(txout, dma64dd_t));
|
||||
|
||||
/* tx flow control */
|
||||
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
|
||||
|
||||
return (0);
|
||||
|
||||
outoftxd:
|
||||
DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
|
||||
PKTFREE(di->osh, p0, TRUE);
|
||||
di->hnddma.txavail = 0;
|
||||
di->hnddma.txnobuf++;
|
||||
return (-1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reclaim next completed txd (txds if using chained buffers) and
|
||||
* return associated packet.
|
||||
* If 'force' is true, reclaim txd(s) and return associated packet
|
||||
* regardless of the value of the hardware "curr" pointer.
|
||||
*/
|
||||
static void *
|
||||
dma64_getnexttxp(dma_info_t *di, bool forceall)
|
||||
{
|
||||
uint start, end, i;
|
||||
void *txp;
|
||||
|
||||
DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
|
||||
|
||||
if (di->ntxd == 0)
|
||||
return (NULL);
|
||||
|
||||
txp = NULL;
|
||||
|
||||
start = di->txin;
|
||||
if (forceall)
|
||||
end = di->txout;
|
||||
else
|
||||
end = B2I(R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
|
||||
|
||||
if ((start == 0) && (end > di->txout))
|
||||
goto bogus;
|
||||
|
||||
for (i = start; i != end && !txp; i = NEXTTXD(i)) {
|
||||
DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) - di->dataoffsetlow),
|
||||
(BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) & D64_CTRL2_BC_MASK),
|
||||
DMA_TX, di->txp[i]);
|
||||
|
||||
W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
|
||||
W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
|
||||
|
||||
txp = di->txp[i];
|
||||
di->txp[i] = NULL;
|
||||
}
|
||||
|
||||
di->txin = i;
|
||||
|
||||
/* tx flow control */
|
||||
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
|
||||
|
||||
return (txp);
|
||||
|
||||
bogus:
|
||||
/*
|
||||
DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
|
||||
start, end, di->txout, forceall));
|
||||
*/
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
static void *
|
||||
dma64_getnextrxp(dma_info_t *di, bool forceall)
|
||||
{
|
||||
uint i;
|
||||
void *rxp;
|
||||
|
||||
/* if forcing, dma engine must be disabled */
|
||||
ASSERT(!forceall || !dma64_rxenabled(di));
|
||||
|
||||
i = di->rxin;
|
||||
|
||||
/* return if no packets posted */
|
||||
if (i == di->rxout)
|
||||
return (NULL);
|
||||
|
||||
/* ignore curr if forceall */
|
||||
if (!forceall &&
|
||||
(i == B2I(R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK, dma64dd_t)))
|
||||
return (NULL);
|
||||
|
||||
/* get the packet pointer that corresponds to the rx descriptor */
|
||||
rxp = di->rxp[i];
|
||||
ASSERT(rxp);
|
||||
di->rxp[i] = NULL;
|
||||
|
||||
/* clear this packet from the descriptor ring */
|
||||
DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) - di->dataoffsetlow),
|
||||
di->rxbufsize, DMA_RX, rxp);
|
||||
|
||||
W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
|
||||
W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
|
||||
|
||||
di->rxin = NEXTRXD(i);
|
||||
|
||||
return (rxp);
|
||||
}
|
||||
|
||||
static bool
|
||||
_dma64_addrext(osl_t *osh, dma64regs_t *dma64regs)
|
||||
{
|
||||
uint32 w;
|
||||
OR_REG(osh, &dma64regs->control, D64_XC_AE);
|
||||
w = R_REG(osh, &dma64regs->control);
|
||||
AND_REG(osh, &dma64regs->control, ~D64_XC_AE);
|
||||
return ((w & D64_XC_AE) == D64_XC_AE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
|
||||
*/
|
||||
static void
|
||||
dma64_txrotate(dma_info_t *di)
|
||||
{
|
||||
uint ad;
|
||||
uint nactive;
|
||||
uint rot;
|
||||
uint old, new;
|
||||
uint32 w;
|
||||
uint first, last;
|
||||
|
||||
ASSERT(dma64_txsuspendedidle(di));
|
||||
|
||||
nactive = _dma_txactive(di);
|
||||
ad = B2I((R_REG(di->osh, &di->d64txregs->status1) & D64_XS1_AD_MASK), dma64dd_t);
|
||||
rot = TXD(ad - di->txin);
|
||||
|
||||
ASSERT(rot < di->ntxd);
|
||||
|
||||
/* full-ring case is a lot harder - don't worry about this */
|
||||
if (rot >= (di->ntxd - nactive)) {
|
||||
DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
|
||||
return;
|
||||
}
|
||||
|
||||
first = di->txin;
|
||||
last = PREVTXD(di->txout);
|
||||
|
||||
/* move entries starting at last and moving backwards to first */
|
||||
for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
|
||||
new = TXD(old + rot);
|
||||
|
||||
/*
|
||||
* Move the tx dma descriptor.
|
||||
* EOT is set only in the last entry in the ring.
|
||||
*/
|
||||
w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl1)) & ~D64_CTRL1_EOT;
|
||||
if (new == (di->ntxd - 1))
|
||||
w |= D64_CTRL1_EOT;
|
||||
W_SM(&di->txd64[new].ctrl1, BUS_SWAP32(w));
|
||||
|
||||
w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl2));
|
||||
W_SM(&di->txd64[new].ctrl2, BUS_SWAP32(w));
|
||||
|
||||
W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
|
||||
W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
|
||||
|
||||
/* zap the old tx dma descriptor address field */
|
||||
W_SM(&di->txd64[old].addrlow, BUS_SWAP32(0xdeadbeef));
|
||||
W_SM(&di->txd64[old].addrhigh, BUS_SWAP32(0xdeadbeef));
|
||||
|
||||
/* move the corresponding txp[] entry */
|
||||
ASSERT(di->txp[new] == NULL);
|
||||
di->txp[new] = di->txp[old];
|
||||
di->txp[old] = NULL;
|
||||
}
|
||||
|
||||
/* update txin and txout */
|
||||
di->txin = ad;
|
||||
di->txout = TXD(di->txout + rot);
|
||||
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
|
||||
|
||||
/* kick the chip */
|
||||
W_REG(di->osh, &di->d64txregs->ptr, I2B(di->txout, dma64dd_t));
|
||||
}
|
||||
|
||||
#endif /* BCMDMA64 */
|
||||
|
||||
uint
|
||||
dma_addrwidth(sb_t *sbh, void *dmaregs)
|
||||
@ -1143,6 +1858,27 @@ dma_addrwidth(sb_t *sbh, void *dmaregs)
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
if (DMA64_CAP) {
|
||||
/* DMA engine is 64-bit capable */
|
||||
if (((sb_coreflagshi(sbh, 0, 0) & SBTMH_DMA64) == SBTMH_DMA64)) {
|
||||
/* backplane are 64 bits capable */
|
||||
#if 0
|
||||
if (sb_backplane64(sbh))
|
||||
/* If bus is System Backplane or PCIE then we can access 64-bits */
|
||||
if ((BUSTYPE(sbh->bustype) == SB_BUS) ||
|
||||
((BUSTYPE(sbh->bustype) == PCI_BUS) &&
|
||||
sbh->buscoretype == SB_PCIE))
|
||||
return (DMADDRWIDTH_64);
|
||||
#endif
|
||||
|
||||
/* DMA64 is always 32 bits capable, AE is always TRUE */
|
||||
#ifdef BCMDMA64
|
||||
ASSERT(_dma64_addrext(osh, (dma64regs_t *)dmaregs));
|
||||
#endif
|
||||
return (DMADDRWIDTH_32);
|
||||
}
|
||||
}
|
||||
|
||||
/* Start checking for 32-bit / 30-bit addressing */
|
||||
dma32regs = (dma32regs_t *)dmaregs;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user