fix the PCI byte lane enable generation code, based on a patch by Chris Dearman

SVN-Revision: 12617
This commit is contained in:
Gabor Juhos 2008-09-17 13:29:47 +00:00
parent 954c24c5ed
commit a43e2d5ac6

View File

@ -59,17 +59,18 @@ static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
/* Byte lane enable bits */
static u8 ble_table[4][4] = {
{0xf, 0xe, 0xd, 0xc},
{0xc, 0x9, 0x3, 0x1},
{0x0, 0x0, 0x0, 0x0},
{0x0, 0x0, 0x0, 0x0},
{0x0, 0xf, 0xf, 0xf},
{0xe, 0xd, 0xb, 0x7},
{0xc, 0xf, 0x3, 0xf},
{0xf, 0xf, 0xf, 0xf},
};
static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
{
u32 t;
t = ble_table[size][where & 3];
t = ble_table[size & 3][where & 3];
BUG_ON(t == 0xf);
t <<= (local) ? 20 : 4;
return t;
}