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ipq806x: force 2nd pci slot into gen1 mode

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According to QSDK and OEM tarballs (checked c2600, r7500v2, r7800) 2nd pci slot (pci1, 2,4 GHz card)) on ap148 based boards should operate in gen1 mode.
EA8500 is an exception and according to GPL pcie0 should operate in gen1 mode.

In previous commit we've added the support for this option, so enable it in DT for affected devices.

QSDK ref:
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?h=release/endive_preview_cc&id=f3b07fe309027c52fc163149500cedddd707c506

While at it move the phy transmit termination offset value into dtsi file as it's platform specific.

Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
This commit is contained in:
Pavel Kubelun 2017-07-06 17:20:18 +03:00 committed by Felix Fietkau
parent 36a96a4493
commit 83499bef73
10 changed files with 17 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
View File

@ -161,12 +161,11 @@
pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};
pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};
nand@1ac00000 {

3
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
View File

@ -346,12 +346,11 @@
pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};
pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};
mdio0: mdio {

1
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
View File

@ -193,6 +193,7 @@
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
force_gen1 = <1>;
};
nand@1ac00000 {

8
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
View File

@ -157,19 +157,17 @@
pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};
pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
};
pcie2: pci@1b900000 {
status = "ok";
phy-tx0-term-offset = <7>;
};
nand@1ac00000 {
status = "ok";

1
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
View File

@ -168,6 +168,7 @@
pcie1: pci@1b700000 {
status = "ok";
force_gen1 = <1>;
};
nand@1ac00000 {

1
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
View File

@ -198,6 +198,7 @@
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
force_gen1 = <1>;
};
nand@1ac00000 {

3
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
View File

@ -259,12 +259,11 @@
pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};
pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};
mdio0: mdio {

6
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
View File

@ -1051,6 +1051,8 @@
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
phy-tx0-term-offset = <7>;
status = "disabled";
};
@ -1103,6 +1105,8 @@
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
phy-tx0-term-offset = <7>;
status = "disabled";
};
@ -1155,6 +1159,8 @@
perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
phy-tx0-term-offset = <7>;
status = "disabled";
};

1
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
View File

@ -229,6 +229,7 @@
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
force_gen1 = <1>;
};
mdio0: mdio {

3
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
View File

@ -299,12 +299,11 @@
pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};
pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};
nand@1ac00000 {