additional avr32 fixes
SVN-Revision: 25556
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82608a62ad
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@ -0,0 +1,32 @@
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--- a/gcc/config/avr32/avr32.c
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+++ b/gcc/config/avr32/avr32.c
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@@ -6501,12 +6501,23 @@ avr32_reorg_optimization (void)
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continue;
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set = single_set (scan);
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- if (set && rtx_equal_p (src_reg, SET_DEST (set)))
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- {
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- link = scan;
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- break;
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- }
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-
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+ // Fix for bug #11763 : the following if condition
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+ // has been modified and else part is included to
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+ // set the link to NULL_RTX.
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+ // if (set && rtx_equal_p (src_reg, SET_DEST (set)))
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+ if (set && (REGNO(src_reg) == REGNO(SET_DEST(set))))
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+ {
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+ if (rtx_equal_p (src_reg, SET_DEST (set)))
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+ {
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+ link = scan;
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+ break;
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+ }
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+ else
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+ {
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+ link = NULL_RTX;
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+ break;
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+ }
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+ }
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}
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15
toolchain/gcc/patches/4.3.5/949-avr32_nan_by_zero_div.patch
Normal file
15
toolchain/gcc/patches/4.3.5/949-avr32_nan_by_zero_div.patch
Normal file
@ -0,0 +1,15 @@
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--- a/gcc/config/avr32/lib1funcs.S
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+++ b/gcc/config/avr32/lib1funcs.S
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@@ -1852,7 +1852,11 @@ __avr32_f64_div_res_subnormal:/* Divide
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mov r10, 0
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ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
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-17: /* Return INF. */
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+17:
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+ /* Check if op1 is zero. */
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+ or r4, r10, r11
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+ breq __avr32_f64_div_op1_zero
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+ /* Return INF. */
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mov r11, lr /*Get correct sign*/
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andh r11, 0x8000, COH
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orh r11, 0x7ff0
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