ath79: Port PowerCloud Systems CR5000 support
Add ath79 arch support for PowerCloud Systems CR5000. Previously supported under ar71xx (however there are some errors in that support; to be fixed shortly). Info: * This board is based on the Atheros DB120 reference design, but doesn't use the on-board switch. Instead it attachs GMAC0 to an AR8327 switch. * It only uses GMAC0 and the WAN is simply a VLAN in the stock firmware. * It has 64MB RAM and 8MB flash. * In the dts version we get rid of using 'open-drain' for the AR8327 LED controls. * As with the platform data version we disable JTAG as this conflicts with one of the pair of GPIO's required for the power/status LED (GPIO2 and GPIO4 are used for this LED). * The pcie card wifi has an EEPROM but gets it's MAC address from the ART partition. * The SoC wifi (2.4 GHz) is all from the ART. * The USB is support comes from the SoC. NB. This is actually an AR9342 rather than AR9344 but we use the 9344 definitions because there are no relevant differences for this board. NB: Building only images that don't support reverting to the old cloud-based firmware as the Skydog cloud service for the CR5000 no longer exists. Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
This commit is contained in:
Daniel F. Dickinson
John Crispin
parent
296ae7ab89
commit
4b93cbd172
@ -28,6 +28,11 @@ case "$board" in
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ucidef_set_led_switch "lan1" "LAN1" "netgear:green:lan1" "switch0" "0x02" "0x0f"
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ucidef_set_led_switch "lan2" "LAN2" "netgear:green:lan2" "switch0" "0x04" "0x0f"
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;;
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"pcs,cr5000")
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ucidef_set_led_usbdev "usb" "USB" "pcs:white:wps" "1-1"
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;;
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"tplink,re450-v2")
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ucidef_set_led_netdev "lan_data" "LAN Data" "tp-link:green:lan_data" "eth0" "tx rx"
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ucidef_set_led_netdev "lan_link" "LAN Link" "tp-link:green:lan_link" "eth0" "link"
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@ -43,6 +43,11 @@ ath79_setup_interfaces()
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"0@eth1" "1:lan" "2:lan" "3:lan:3" "4:lan:4"
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;;
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"pcs,cr5000")
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ucidef_add_switch "switch0" \
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"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan"
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;;
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"tplink,tl-archer-c7-v2")
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ucidef_set_interfaces_lan_wan "eth1.1" "eth0.2"
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ucidef_add_switch "switch0" \
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226
target/linux/ath79/dts/ar9344_pcs_cr5000.dts
Normal file
226
target/linux/ath79/dts/ar9344_pcs_cr5000.dts
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@ -0,0 +1,226 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "ar9344.dtsi"
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/ {
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model = "PowerCloud Systems CR5000";
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compatible = "pcs,cr5000", "qca,ar9344";
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aliases {
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serial0 = &uart;
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led-status = &status;
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&jtag_disable_pins>;
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reset {
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label = "Reset button";
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linux,code = <KEY_RESTART>;
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gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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wps {
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label = "WPS button";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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leds {
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compatible = "gpio-leds";
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status: power {
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label = "pcs:amber:power";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>,
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<&gpio 4 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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wlan2g {
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label = "pcs:blue:wlan";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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default-state = "off";
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linux,default-trigger = "phy0tpt";
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};
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wps_white {
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label = "pcs:white:wps";
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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};
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};
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&ref {
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clock-frequency = <25000000>;
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};
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&uart {
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status = "okay";
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};
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&gpio {
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status = "okay";
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};
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&spi {
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num-cs = <1>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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uboot: partition@0 {
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label = "u-boot";
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reg = <0x000000 0x040000>;
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read-only;
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};
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partition@40000 {
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label = "u-boot-env";
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reg = <0x040000 0x010000>;
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read-only;
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};
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partition@50000 {
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label = "firmware";
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reg = <0x050000 0x07a0000>;
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};
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art: partition@7f0000 {
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label = "art";
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reg = <0x7f0000 0x010000>;
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read-only;
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};
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};
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};
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};
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&usb {
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status = "okay";
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port@1 {
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reg = <1>;
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#trigger-source-cells = <0>;
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hub_port1: port@1 {
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reg = <1>;
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#trigger-source-cells = <0>;
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};
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};
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};
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&usb_phy {
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status = "okay";
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};
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&pcie {
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status = "okay";
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ath9k: wifi@168c,0030 {
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compatible = "168c,0030";
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mtd-mac-address = <&art 0x5002>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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&mdio0 {
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status = "okay";
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phy-mask = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "rgmii";
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qca,ar8327-initvals = <
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0x04 0x07600000 /* PORT0 PAD MODE CTRL */
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0x10 0x81000080 /* POWER_ON_STRAP */
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0x50 0xcc35cc35 /* LED_CTRL0 */
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0x54 0xca35ca35 /* LED_CTRL1 */
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0x58 0xc935c935 /* LED_CTRL2 */
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0x5c 0x03ffff00 /* LED_CTRL3 */
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0x7c 0x0000007e /* PORT0_STATUS */
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>;
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};
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};
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ð0 {
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status = "okay";
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/* default for ar934x, except for 1000M */
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pll-data = <0x06000000 0x00000101 0x00001616>;
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mtd-mac-address = <&art 0x0>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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aliases {
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ag0 = ð1;
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};
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port@0 {
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compatible = "swconfig,port";
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swconfig,segment = "lan";
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swconfig,portmap = <1 1>;
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};
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port@1 {
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compatible = "swconfig,port";
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swconfig,segment = "lan";
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swconfig,portmap = <2 2>;
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};
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port@2 {
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compatible = "swconfig,port";
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swconfig,segment = "lan";
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swconfig,portmap = <3 3>;
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};
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port@3 {
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compatible = "swconfig,port";
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swconfig,segment = "lan";
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swconfig,portmap = <4 4>;
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};
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port@4 {
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compatible = "swconfig,port";
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swconfig,segment = "wan";
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swconfig,portmap = <5 5>;
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};
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};
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&wmac {
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status = "okay";
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mtd-cal-data = <&art 0x1000>;
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mtd-mac-address = <&art 0x1002>;
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};
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@ -66,6 +66,16 @@ define Device/openmesh_om5p-ac-v2
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endef
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TARGET_DEVICES += openmesh_om5p-ac-v2
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define Device/pcs_cr5000
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ATH_SOC := ar9344
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DEVICE_TITLE := PowerCloud Systems CR5000
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DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-usb-core
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IMAGE_SIZE := 7808k
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IMAGES := sysupgrade.bin
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SUPPORTED_DEVICES += cr5000
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endef
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TARGET_DEVICES += pcs_cr5000
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define Device/netgear_wndr3800
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ATH_SOC := ar7161
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DEVICE_TITLE := NETGEAR WNDR3800
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