From 43d1d88510621801d66a0a7f46f4c4f44d89633a Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Wed, 18 Mar 2020 19:04:13 +0100 Subject: [PATCH] tegra: correct cpu subtype Tegra 2 processors have only 16 double-precision registers. The change introduced by 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") switched accidentally the toolchain for tegra target to cpu type with 32 double-precision registers. This stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in unusable image, in which kernel will kill userspace as soon as it causing "Illegal instruction". Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes: 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak --- target/linux/tegra/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/tegra/Makefile b/target/linux/tegra/Makefile index 0b48fc16ba..5dd4d43984 100644 --- a/target/linux/tegra/Makefile +++ b/target/linux/tegra/Makefile @@ -11,7 +11,7 @@ BOARD := tegra BOARDNAME := NVIDIA Tegra FEATURES := audio boot-part display ext4 fpu gpio pci pcie rootfs-part rtc squashfs usb CPU_TYPE := cortex-a9 -CPU_SUBTYPE := vfpv3 +CPU_SUBTYPE := vfpv3-d16 KERNEL_PATCHVER := 5.4 KERNEL_TESTING_PATCHVER := 5.4