From 26c84b2e46caba1ae17bc82a533c99eee65e7004 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Sat, 1 May 2021 14:17:11 -0400 Subject: [PATCH] ramips: mt7620: fix RGMII TXID PHY mode the register bits for TX delay and RX delay are opposites: when TX delay bit is set, delay is enabled when RX delay bit is set, delay is disabled So, when both bits are unset, it is RX delay and when both bits are set, it is TX delay Note: TXID is the default RGMII mode of the SOC Fixes: 5410a8e2959a ("ramips: mt7620: add rgmii delays support") Signed-off-by: Michael Pratt --- .../linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c index 4d012afa14..c9104aa375 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c @@ -205,7 +205,7 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np) break; case PHY_INTERFACE_MODE_RGMII_TXID: mask = 0; - val_delay &= ~GSW_REG_GPCx_TXDELAY; + val_delay |= GSW_REG_GPCx_TXDELAY; val_delay |= GSW_REG_GPCx_RXDELAY; break; case PHY_INTERFACE_MODE_MII: