diff --git a/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch b/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch
new file mode 100644
index 0000000000..967045db02
--- /dev/null
+++ b/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch
@@ -0,0 +1,25 @@
+From 08b085a07efe12568d86dff064e6f089e2971744 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 25 May 2015 22:39:50 +0200
+Subject: gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs
+
+0x3 only masks two bits, but three bits have to be allowed. This fixes
+GPHY0 LED2 (which is the highest bit of phy2) on my board.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Acked-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+
+diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c
+index 202361e..6d4148f 100644
+--- a/drivers/gpio/gpio-stp-xway.c
++++ b/drivers/gpio/gpio-stp-xway.c
+@@ -58,7 +58,7 @@
+ #define XWAY_STP_ADSL_MASK	0x3
+ 
+ /* 2 groups of 3 bits can be driven by the phys */
+-#define XWAY_STP_PHY_MASK	0x3
++#define XWAY_STP_PHY_MASK	0x7
+ #define XWAY_STP_PHY1_SHIFT	27
+ #define XWAY_STP_PHY2_SHIFT	15
+