ipq806x: replace phy dwc3 patch with upstream version
- Replace dwc3 phy patch with upstream version - Rework the dts to use the upstream bindings - Update changed config flags - Rename module to reflect config name Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> [fix qcom,tx-deamp_3_5db typo, refresh patches, rename kmod] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Tested-by: Paul Blazejowski <paulb@blazebox.homeip.net> [R7800]
This commit is contained in:
Ansuel Smith
Adrian Schmutzler
parent
e5eeb34a8c
commit
0c45ad41e1
@ -70,22 +70,22 @@ endef
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$(eval $(call KernelPackage,usb-phy-nop))
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define KernelPackage/usb-phy-qcom-dwc3
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TITLE:=DWC3 USB QCOM PHY driver
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define KernelPackage/phy-qcom-ipq806x-usb
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TITLE:=Qualcomm IPQ806x DWC3 USB PHY driver
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DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x)
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KCONFIG:= CONFIG_PHY_QCOM_DWC3
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KCONFIG:= CONFIG_PHY_QCOM_IPQ806X_USB
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FILES:= \
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$(LINUX_DIR)/drivers/phy/qualcomm/phy-qcom-dwc3.ko
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AUTOLOAD:=$(call AutoLoad,45,phy-qcom-dwc3,1)
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$(LINUX_DIR)/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.ko
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AUTOLOAD:=$(call AutoLoad,45,phy-qcom-ipq806x-usb,1)
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$(call AddDepends/usb)
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endef
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define KernelPackage/usb-phy-qcom-dwc3/description
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define KernelPackage/phy-qcom-ipq806x-usb/description
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This driver provides support for the integrated DesignWare
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USB3 IP Core within the QCOM SoCs.
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endef
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$(eval $(call KernelPackage,usb-phy-qcom-dwc3))
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$(eval $(call KernelPackage,phy-qcom-ipq806x-usb))
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define KernelPackage/phy-ath79-usb
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@ -19,7 +19,7 @@ DEFAULT_PACKAGES += \
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kmod-leds-gpio kmod-gpio-button-hotplug swconfig \
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kmod-ata-ahci kmod-ata-ahci-platform \
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kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \
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kmod-usb-phy-qcom-dwc3 kmod-usb3 kmod-usb-dwc3-qcom \
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kmod-phy-qcom-ipq806x-usb kmod-usb3 kmod-usb-dwc3-qcom \
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kmod-ath10k-ct wpad-basic \
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uboot-envtools
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@ -31,13 +31,13 @@
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};
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&ss_phy_0 {
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rx_eq = <2>;
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tx_deamp_3_5db = <32>;
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mpll = <0xa0>;
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qcom,rx-eq = <2>;
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qcom,tx-deamp_3_5db = <32>;
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qcom,mpll = <5>;
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};
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&ss_phy_1 {
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rx_eq = <2>;
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tx_deamp_3_5db = <32>;
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mpll = <0xa0>;
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qcom,rx-eq = <2>;
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qcom,tx-deamp_3_5db = <32>;
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qcom,mpll = <5>;
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};
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@ -46,15 +46,15 @@
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};
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&ss_phy_0 {
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rx_eq = <2>;
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tx_deamp_3_5db = <32>;
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mpll = <0xa0>;
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qcom,rx-eq = <2>;
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qcom,tx-deamp_3_5db = <32>;
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qcom,mpll = <5>;
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};
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&ss_phy_1 {
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rx_eq = <2>;
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tx_deamp_3_5db = <32>;
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mpll = <0xa0>;
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qcom,rx-eq = <2>;
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qcom,tx-deamp_3_5db = <32>;
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qcom,mpll = <5>;
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};
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&opp_table0 {
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@ -1,614 +0,0 @@
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From b9004f4fd23e4c614d71c972f3a9311665480e29 Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Thu, 9 Mar 2017 08:19:18 +0100
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Subject: [PATCH 32/69] phy: add qcom dwc3 phy
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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--- a/drivers/phy/qualcomm/Kconfig
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+++ b/drivers/phy/qualcomm/Kconfig
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@@ -91,3 +91,15 @@ config PHY_QCOM_USB_HSIC
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select GENERIC_PHY
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help
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Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
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+
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+config PHY_QCOM_DWC3
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+ tristate "QCOM DWC3 USB PHY support"
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+ depends on ARCH_QCOM
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+ depends on HAS_IOMEM
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+ depends on OF
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+ select GENERIC_PHY
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+ help
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+ This option enables support for the Synopsis PHYs present inside the
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+ Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS
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+ PHY controllers.
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+
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--- a/drivers/phy/qualcomm/Makefile
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+++ b/drivers/phy/qualcomm/Makefile
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@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-
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obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
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obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
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obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
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+obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o
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--- /dev/null
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+++ b/drivers/phy/qualcomm/phy-qcom-dwc3.c
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@@ -0,0 +1,578 @@
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+/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+* This program is distributed in the hope that it will be useful,
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+* but WITHOUT ANY WARRANTY; without even the implied warranty of
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+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+* GNU General Public License for more details.
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+*/
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+
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/phy/phy.h>
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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+#include <linux/regmap.h>
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+#include <linux/mfd/syscon.h>
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+
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+/**
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+ * USB QSCRATCH Hardware registers
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+ */
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+#define QSCRATCH_GENERAL_CFG (0x08)
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+#define HSUSB_PHY_CTRL_REG (0x10)
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+
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+/* PHY_CTRL_REG */
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+#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
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+#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
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+#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
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+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
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+#define HSUSB_CTRL_USE_CLKCORE BIT(18)
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+#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
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+#define HSUSB_CTRL_COMMONONN BIT(11)
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+#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
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+#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
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+#define HSUSB_CTRL_CLAMP_EN BIT(7)
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+#define HSUSB_CTRL_RETENABLEN BIT(1)
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+#define HSUSB_CTRL_POR BIT(0)
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+
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+/* QSCRATCH_GENERAL_CFG */
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+#define HSUSB_GCFG_XHCI_REV BIT(2)
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+
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+/**
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+ * USB QSCRATCH Hardware registers
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+ */
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+#define SSUSB_PHY_CTRL_REG (0x30)
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+#define SSUSB_PHY_PARAM_CTRL_1 (0x34)
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+#define SSUSB_PHY_PARAM_CTRL_2 (0x38)
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+#define CR_PROTOCOL_DATA_IN_REG (0x3c)
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+#define CR_PROTOCOL_DATA_OUT_REG (0x40)
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+#define CR_PROTOCOL_CAP_ADDR_REG (0x44)
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+#define CR_PROTOCOL_CAP_DATA_REG (0x48)
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+#define CR_PROTOCOL_READ_REG (0x4c)
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+#define CR_PROTOCOL_WRITE_REG (0x50)
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+
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+/* PHY_CTRL_REG */
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+#define SSUSB_CTRL_REF_USE_PAD BIT(28)
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+#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
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+#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
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+#define SSUSB_CTRL_SS_PHY_EN BIT(8)
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+#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
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+
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+/* SSPHY control registers - Does this need 0x30? */
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+#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane)
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+#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane)
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+
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+/* SSPHY SoC version specific values */
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+#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
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+#define SSPHY_TX_DEEMPH_3_5DB 23 /* Override value for transmit
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+ preemphasis */
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+#define SSPHY_MPLL_VALUE 0 /* Override value for mpll */
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+
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+/* QSCRATCH PHY_PARAM_CTRL1 fields */
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+#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK 0x07f00000u
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+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK 0x000fc000u
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+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK 0x00003f00u
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+#define PHY_PARAM_CTRL1_LOS_BIAS_MASK 0x000000f8u
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+
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+#define PHY_PARAM_CTRL1_MASK \
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+ (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
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+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
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+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
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+ PHY_PARAM_CTRL1_LOS_BIAS_MASK)
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+
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+#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
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+ (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
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+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
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+ (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
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+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
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+ (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
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+#define PHY_PARAM_CTRL1_LOS_BIAS(x) \
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+ (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
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+
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+/* RX OVRD IN HI bits */
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+#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
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+#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
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+#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
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+#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700
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+#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8
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+#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
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+#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
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+#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
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+#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018
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+#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
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+#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003
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+
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+/* TX OVRD DRV LO register bits */
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+#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F
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+#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80
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+#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7
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+#define TX_OVRD_DRV_LO_EN BIT(14)
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+
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+/* SS CAP register bits */
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+#define SS_CR_CAP_ADDR_REG BIT(0)
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+#define SS_CR_CAP_DATA_REG BIT(0)
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+#define SS_CR_READ_REG BIT(0)
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+#define SS_CR_WRITE_REG BIT(0)
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+
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+struct qcom_dwc3_usb_phy {
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+ struct regmap *base;
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+ struct device *dev;
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+ struct clk *xo_clk;
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+ struct clk *ref_clk;
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+ u32 rx_eq;
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+ u32 tx_deamp_3_5db;
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+ u32 mpll;
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+};
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+
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+struct qcom_dwc3_phy_drvdata {
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+ struct phy_ops ops;
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+ u32 clk_rate;
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+};
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+
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+/**
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+ * Write register and read back masked value to confirm it is written
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+ *
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+ * @base - QCOM DWC3 PHY base virtual address.
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+ * @offset - register offset.
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+ * @mask - register bitmask specifying what should be updated
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+ * @val - value to write.
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+ */
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+static inline void qcom_dwc3_phy_write_readback(
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+ struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
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+ const u32 mask, u32 val)
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+{
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+ u32 write_val, tmp;
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+
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+ tmp = regmap_read(phy_dwc3->base, offset, &tmp);
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+ tmp &= ~mask; /* retain other bits */
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+ write_val = tmp | val;
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+
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+ regmap_write(phy_dwc3->base, offset, write_val);
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+
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+ /* Read back to see if val was written */
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+ regmap_read(phy_dwc3->base, offset, &tmp);
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+ tmp &= mask; /* clear other bits */
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+
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+ if (tmp != val)
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+ dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
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+ val, offset);
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+}
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+
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+static int wait_for_latch(struct regmap *base, u32 addr)
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+{
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+ u32 retry = 10, data;
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+
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+ while (true) {
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+ regmap_read(base, addr, &data);
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+ if (!data)
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+ break;
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+
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+ if (--retry == 0)
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+ return -ETIMEDOUT;
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+
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+ usleep_range(10, 20);
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+ }
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+
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+ return 0;
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+}
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+
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+/**
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+ * Write SSPHY register
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+ *
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+ * @base - QCOM DWC3 PHY base virtual address.
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+ * @addr - SSPHY address to write.
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+ * @val - value to write.
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+ */
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+static int qcom_dwc3_ss_write_phycreg(struct qcom_dwc3_usb_phy *phy_dwc3,
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+ u32 addr, u32 val)
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+{
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+ int ret;
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+
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+ regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, addr);
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+ regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG, SS_CR_CAP_ADDR_REG);
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+
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+ ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG);
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+ if (ret)
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+ goto err_wait;
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+
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+ regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, val);
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+ regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG, SS_CR_CAP_DATA_REG);
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+
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+ ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG);
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+ if (ret)
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+ goto err_wait;
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+
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+ regmap_write(phy_dwc3->base, CR_PROTOCOL_WRITE_REG, SS_CR_WRITE_REG);
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+
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+ ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_WRITE_REG);
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+
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+err_wait:
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+ if (ret)
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+ dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
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+ return ret;
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+}
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+
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+/**
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+ * Read SSPHY register.
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+ *
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+ * @base - QCOM DWC3 PHY base virtual address.
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+ * @addr - SSPHY address to read.
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+ */
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+static int qcom_dwc3_ss_read_phycreg(struct regmap *base, u32 addr, u32 *val)
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+{
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+ int ret;
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+
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+ regmap_write(base, CR_PROTOCOL_DATA_IN_REG, addr);
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+ regmap_write(base, CR_PROTOCOL_CAP_ADDR_REG, SS_CR_CAP_ADDR_REG);
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+
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+ ret = wait_for_latch(base, CR_PROTOCOL_CAP_ADDR_REG);
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+ if (ret)
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+ goto err_wait;
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+
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+ /*
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+ * Due to hardware bug, first read of SSPHY register might be
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+ * incorrect. Hence as workaround, SW should perform SSPHY register
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+ * read twice, but use only second read and ignore first read.
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+ */
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+ regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG);
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+
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+ ret = wait_for_latch(base, CR_PROTOCOL_READ_REG);
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+ if (ret)
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+ goto err_wait;
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+
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+ /* throwaway read */
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+ regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, &ret);
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+
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+ regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG);
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+
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+ ret = wait_for_latch(base, CR_PROTOCOL_READ_REG);
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+ if (ret)
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+ goto err_wait;
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+
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+ regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, val);
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+
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+err_wait:
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+ return ret;
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+}
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+
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+static int qcom_dwc3_hs_phy_init(struct phy *phy)
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+{
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+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
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+ int ret;
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+ u32 val;
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+
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+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
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+ if (ret)
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+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
|
||||
+ * enable clamping, and disable RETENTION (power-on default is ENABLED)
|
||||
+ */
|
||||
+ val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
|
||||
+ HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
|
||||
+ HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
|
||||
+ HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
|
||||
+ HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
|
||||
+
|
||||
+ /* use core clock if external reference is not present */
|
||||
+ if (!phy_dwc3->xo_clk)
|
||||
+ val |= HSUSB_CTRL_USE_CLKCORE;
|
||||
+
|
||||
+ regmap_write(phy_dwc3->base, HSUSB_PHY_CTRL_REG, val);
|
||||
+ usleep_range(2000, 2200);
|
||||
+
|
||||
+ /* Disable (bypass) VBUS and ID filters */
|
||||
+ regmap_write(phy_dwc3->base, QSCRATCH_GENERAL_CFG, HSUSB_GCFG_XHCI_REV);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qcom_dwc3_hs_phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_disable_unprepare(phy_dwc3->ref_clk);
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qcom_dwc3_ss_phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+ u32 data = 0;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* reset phy */
|
||||
+ regmap_read(phy_dwc3->base, SSUSB_PHY_CTRL_REG, &data);
|
||||
+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG,
|
||||
+ data | SSUSB_CTRL_SS_PHY_RESET);
|
||||
+ usleep_range(2000, 2200);
|
||||
+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data);
|
||||
+
|
||||
+ /* clear REF_PAD if we don't have XO clk */
|
||||
+ if (!phy_dwc3->xo_clk)
|
||||
+ data &= ~SSUSB_CTRL_REF_USE_PAD;
|
||||
+ else
|
||||
+ data |= SSUSB_CTRL_REF_USE_PAD;
|
||||
+
|
||||
+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data);
|
||||
+
|
||||
+ /* wait for ref clk to become stable, this can take up to 30ms */
|
||||
+ msleep(30);
|
||||
+
|
||||
+ data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
|
||||
+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data);
|
||||
+
|
||||
+ /*
|
||||
+ * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
|
||||
+ * in HS mode instead of SS mode. Workaround it by asserting
|
||||
+ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
|
||||
+ */
|
||||
+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x102D, &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data |= (1 << 7);
|
||||
+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x102D, data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x1010, &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~0xff0;
|
||||
+ data |= 0x20;
|
||||
+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x1010, data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ /*
|
||||
+ * Fix RX Equalization setting as follows
|
||||
+ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
|
||||
+ */
|
||||
+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
|
||||
+ SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
|
||||
+ data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
|
||||
+ data |= phy_dwc3->rx_eq << RX_OVRD_IN_HI_RX_EQ_SHIFT;
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
|
||||
+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ /*
|
||||
+ * Set EQ and TX launch amplitudes as follows
|
||||
+ * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
|
||||
+ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
|
||||
+ * LANE0.TX_OVRD_DRV_LO.EN set to 1.
|
||||
+ */
|
||||
+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
|
||||
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
|
||||
+ data |= phy_dwc3->tx_deamp_3_5db << TX_OVRD_DRV_LO_PREEMPH_SHIFT;
|
||||
+ data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
|
||||
+ data |= 0x6E;
|
||||
+ data |= TX_OVRD_DRV_LO_EN;
|
||||
+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x30, phy_dwc3->mpll);
|
||||
+
|
||||
+ /*
|
||||
+ * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
|
||||
+ * TX_FULL_SWING [26:20] amplitude to 110
|
||||
+ * TX_DEEMPH_6DB [19:14] to 32
|
||||
+ * TX_DEEMPH_3_5DB [13:8] set based on SoC version
|
||||
+ * LOS_BIAS [7:3] to 9
|
||||
+ */
|
||||
+ regmap_read(phy_dwc3->base, SSUSB_PHY_PARAM_CTRL_1, &data);
|
||||
+
|
||||
+ data &= ~PHY_PARAM_CTRL1_MASK;
|
||||
+
|
||||
+ data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
|
||||
+ PHY_PARAM_CTRL1_LOS_BIAS(0x9);
|
||||
+
|
||||
+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
|
||||
+ PHY_PARAM_CTRL1_MASK, data);
|
||||
+
|
||||
+err_phy_trans:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int qcom_dwc3_ss_phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+
|
||||
+ /* Sequence to put SSPHY in low power state:
|
||||
+ * 1. Clear REF_PHY_EN in PHY_CTRL_REG
|
||||
+ * 2. Clear REF_USE_PAD in PHY_CTRL_REG
|
||||
+ * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
|
||||
+ */
|
||||
+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_SS_PHY_EN, 0x0);
|
||||
+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_REF_USE_PAD, 0x0);
|
||||
+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_TEST_POWERDOWN, 0x0);
|
||||
+
|
||||
+ clk_disable_unprepare(phy_dwc3->ref_clk);
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = {
|
||||
+ .ops = {
|
||||
+ .init = qcom_dwc3_hs_phy_init,
|
||||
+ .exit = qcom_dwc3_hs_phy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+ .clk_rate = 60000000,
|
||||
+};
|
||||
+
|
||||
+static const struct qcom_dwc3_phy_drvdata qcom_dwc3_ss_drvdata = {
|
||||
+ .ops = {
|
||||
+ .init = qcom_dwc3_ss_phy_init,
|
||||
+ .exit = qcom_dwc3_ss_phy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+ .clk_rate = 125000000,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id qcom_dwc3_phy_table[] = {
|
||||
+ { .compatible = "qcom,dwc3-hs-usb-phy", .data = &qcom_dwc3_hs_drvdata },
|
||||
+ { .compatible = "qcom,dwc3-ss-usb-phy", .data = &qcom_dwc3_ss_drvdata },
|
||||
+ { /* Sentinel */ }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table);
|
||||
+
|
||||
+static int qcom_dwc3_phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3;
|
||||
+ struct phy_provider *phy_provider;
|
||||
+ struct phy *generic_phy;
|
||||
+ struct resource *res;
|
||||
+ const struct of_device_id *match;
|
||||
+ const struct qcom_dwc3_phy_drvdata *data;
|
||||
+ struct device_node *np;
|
||||
+
|
||||
+ phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
|
||||
+ if (!phy_dwc3)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ match = of_match_node(qcom_dwc3_phy_table, pdev->dev.of_node);
|
||||
+ data = match->data;
|
||||
+
|
||||
+ phy_dwc3->dev = &pdev->dev;
|
||||
+
|
||||
+ phy_dwc3->base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
|
||||
+ if (IS_ERR_OR_NULL(phy_dwc3->base))
|
||||
+ return PTR_ERR_OR_ZERO(phy_dwc3->base) ? : -EINVAL;
|
||||
+
|
||||
+ phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
|
||||
+ if (IS_ERR(phy_dwc3->ref_clk)) {
|
||||
+ dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
|
||||
+ return PTR_ERR(phy_dwc3->ref_clk);
|
||||
+ }
|
||||
+
|
||||
+ clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
|
||||
+
|
||||
+ phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
|
||||
+ if (IS_ERR(phy_dwc3->xo_clk)) {
|
||||
+ dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
|
||||
+ phy_dwc3->xo_clk = NULL;
|
||||
+ }
|
||||
+
|
||||
+ /* Parse device node to probe HSIO settings */
|
||||
+ np = of_node_get(pdev->dev.of_node);
|
||||
+ if (!of_compat_cmp(match->compatible, "qcom,dwc3-ss-usb-phy",
|
||||
+ strlen(match->compatible))) {
|
||||
+
|
||||
+ if (of_property_read_u32(np, "rx_eq", &phy_dwc3->rx_eq) ||
|
||||
+ of_property_read_u32(np, "tx_deamp_3_5db",
|
||||
+ &phy_dwc3->tx_deamp_3_5db) ||
|
||||
+ of_property_read_u32(np, "mpll", &phy_dwc3->mpll)) {
|
||||
+
|
||||
+ dev_err(phy_dwc3->dev, "cannot get HSIO settings from device node, using default values\n");
|
||||
+
|
||||
+ /* Default HSIO settings */
|
||||
+ phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
|
||||
+ phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
|
||||
+ phy_dwc3->mpll = SSPHY_MPLL_VALUE;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node,
|
||||
+ &data->ops);
|
||||
+
|
||||
+ if (IS_ERR(generic_phy))
|
||||
+ return PTR_ERR(generic_phy);
|
||||
+
|
||||
+ phy_set_drvdata(generic_phy, phy_dwc3);
|
||||
+ platform_set_drvdata(pdev, phy_dwc3);
|
||||
+
|
||||
+ phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
|
||||
+ of_phy_simple_xlate);
|
||||
+
|
||||
+ if (IS_ERR(phy_provider))
|
||||
+ return PTR_ERR(phy_provider);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver qcom_dwc3_phy_driver = {
|
||||
+ .probe = qcom_dwc3_phy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "qcom-dwc3-usb-phy",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = qcom_dwc3_phy_table,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(qcom_dwc3_phy_driver);
|
||||
+
|
||||
+MODULE_ALIAS("platform:phy-qcom-dwc3");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
|
||||
+MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
|
||||
+MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");
|
||||
@ -1,29 +0,0 @@
|
||||
--- a/drivers/phy/qualcomm/phy-qcom-dwc3.c
|
||||
+++ b/drivers/phy/qualcomm/phy-qcom-dwc3.c
|
||||
@@ -491,7 +491,6 @@ static int qcom_dwc3_phy_probe(struct pl
|
||||
struct qcom_dwc3_usb_phy *phy_dwc3;
|
||||
struct phy_provider *phy_provider;
|
||||
struct phy *generic_phy;
|
||||
- struct resource *res;
|
||||
const struct of_device_id *match;
|
||||
const struct qcom_dwc3_phy_drvdata *data;
|
||||
struct device_node *np;
|
||||
@@ -505,7 +504,17 @@ static int qcom_dwc3_phy_probe(struct pl
|
||||
|
||||
phy_dwc3->dev = &pdev->dev;
|
||||
|
||||
- phy_dwc3->base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
|
||||
+ np = of_parse_phandle(pdev->dev.of_node, "regmap", 0);
|
||||
+ if (!np)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ if (!of_device_is_compatible(np, "syscon"))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ phy_dwc3->base = device_node_to_regmap(np);
|
||||
+
|
||||
+ of_node_put(np);
|
||||
+
|
||||
if (IS_ERR_OR_NULL(phy_dwc3->base))
|
||||
return PTR_ERR_OR_ZERO(phy_dwc3->base) ? : -EINVAL;
|
||||
|
||||
@ -718,16 +718,16 @@
|
||||
+ };
|
||||
+
|
||||
+ hs_phy_0: hs_phy_0 {
|
||||
+ compatible = "qcom,dwc3-hs-usb-phy";
|
||||
+ regmap = <&usb3_0>;
|
||||
+ compatible = "qcom,ipq806x-usb-phy-hs";
|
||||
+ reg = <0x110f8800 0x30>;
|
||||
+ clocks = <&gcc USB30_0_UTMI_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ss_phy_0: ss_phy_0 {
|
||||
+ compatible = "qcom,dwc3-ss-usb-phy";
|
||||
+ regmap = <&usb3_0>;
|
||||
+ compatible = "qcom,ipq806x-usb-phy-ss";
|
||||
+ reg = <0x110f8830 0x30>;
|
||||
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
@ -760,16 +760,16 @@
|
||||
+ };
|
||||
+
|
||||
+ hs_phy_1: hs_phy_1 {
|
||||
+ compatible = "qcom,dwc3-hs-usb-phy";
|
||||
+ regmap = <&usb3_1>;
|
||||
+ compatible = "qcom,ipq806x-usb-phy-hs";
|
||||
+ reg = <0x100f8800 0x30>;
|
||||
+ clocks = <&gcc USB30_1_UTMI_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ss_phy_1: ss_phy_1 {
|
||||
+ compatible = "qcom,dwc3-ss-usb-phy";
|
||||
+ regmap = <&usb3_1>;
|
||||
+ compatible = "qcom,ipq806x-usb-phy-ss";
|
||||
+ reg = <0x100f8830 0x30>;
|
||||
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
|
||||
@ -0,0 +1,621 @@
|
||||
From ef19b117b83466e1c030368101a24367a34be7f0 Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Fri, 17 Jul 2020 15:16:31 +0200
|
||||
Subject: phy: qualcomm: add qcom ipq806x dwc usb phy driver
|
||||
|
||||
This has lost in the original push for the dwc3 qcom driver.
|
||||
This is needed for ipq806x SoC as without this the usb ports
|
||||
doesn't work at all.
|
||||
|
||||
Signed-off-by: Andy Gross <agross@codeaurora.org>
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Tested-by: Jonathan McDowell <noodles@earth.li>
|
||||
Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
|
||||
Light modification to Kconfig as some config are missing in kernel 5.4
|
||||
|
||||
drivers/phy/qualcomm/Kconfig | 10 +
|
||||
drivers/phy/qualcomm/Makefile | 1 +
|
||||
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 571 ++++++++++++++++++++++++++++
|
||||
3 files changed, 582 insertions(+)
|
||||
create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
|
||||
|
||||
--- a/drivers/phy/qualcomm/Kconfig
|
||||
+++ b/drivers/phy/qualcomm/Kconfig
|
||||
@@ -91,3 +91,13 @@ config PHY_QCOM_USB_HSIC
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
|
||||
+
|
||||
+config PHY_QCOM_IPQ806X_USB
|
||||
+ tristate "Qualcomm IPQ806x DWC3 USB PHY driver"
|
||||
+ depends on HAS_IOMEM
|
||||
+ depends on OF && (ARCH_QCOM || COMPILE_TEST)
|
||||
+ select GENERIC_PHY
|
||||
+ help
|
||||
+ This option enables support for the Synopsis PHYs present inside the
|
||||
+ Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
|
||||
+ both HS and SS PHY controllers.
|
||||
--- a/drivers/phy/qualcomm/Makefile
|
||||
+++ b/drivers/phy/qualcomm/Makefile
|
||||
@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-
|
||||
obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
|
||||
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
|
||||
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
|
||||
+obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
|
||||
@@ -0,0 +1,571 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+
|
||||
+/* USB QSCRATCH Hardware registers */
|
||||
+#define QSCRATCH_GENERAL_CFG (0x08)
|
||||
+#define HSUSB_PHY_CTRL_REG (0x10)
|
||||
+
|
||||
+/* PHY_CTRL_REG */
|
||||
+#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
|
||||
+#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
|
||||
+#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
|
||||
+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
|
||||
+#define HSUSB_CTRL_USE_CLKCORE BIT(18)
|
||||
+#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
|
||||
+#define HSUSB_CTRL_COMMONONN BIT(11)
|
||||
+#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
|
||||
+#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
|
||||
+#define HSUSB_CTRL_CLAMP_EN BIT(7)
|
||||
+#define HSUSB_CTRL_RETENABLEN BIT(1)
|
||||
+#define HSUSB_CTRL_POR BIT(0)
|
||||
+
|
||||
+/* QSCRATCH_GENERAL_CFG */
|
||||
+#define HSUSB_GCFG_XHCI_REV BIT(2)
|
||||
+
|
||||
+/* USB QSCRATCH Hardware registers */
|
||||
+#define SSUSB_PHY_CTRL_REG (0x00)
|
||||
+#define SSUSB_PHY_PARAM_CTRL_1 (0x04)
|
||||
+#define SSUSB_PHY_PARAM_CTRL_2 (0x08)
|
||||
+#define CR_PROTOCOL_DATA_IN_REG (0x0c)
|
||||
+#define CR_PROTOCOL_DATA_OUT_REG (0x10)
|
||||
+#define CR_PROTOCOL_CAP_ADDR_REG (0x14)
|
||||
+#define CR_PROTOCOL_CAP_DATA_REG (0x18)
|
||||
+#define CR_PROTOCOL_READ_REG (0x1c)
|
||||
+#define CR_PROTOCOL_WRITE_REG (0x20)
|
||||
+
|
||||
+/* PHY_CTRL_REG */
|
||||
+#define SSUSB_CTRL_REF_USE_PAD BIT(28)
|
||||
+#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
|
||||
+#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
|
||||
+#define SSUSB_CTRL_SS_PHY_EN BIT(8)
|
||||
+#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
|
||||
+
|
||||
+/* SSPHY control registers - Does this need 0x30? */
|
||||
+#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * (lane))
|
||||
+#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * (lane))
|
||||
+
|
||||
+/* SSPHY SoC version specific values */
|
||||
+#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
|
||||
+/* Override value for transmit preemphasis */
|
||||
+#define SSPHY_TX_DEEMPH_3_5DB 23
|
||||
+/* Override value for mpll */
|
||||
+#define SSPHY_MPLL_VALUE 0
|
||||
+
|
||||
+/* QSCRATCH PHY_PARAM_CTRL1 fields */
|
||||
+#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK GENMASK(26, 19)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK GENMASK(19, 13)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK GENMASK(13, 7)
|
||||
+#define PHY_PARAM_CTRL1_LOS_BIAS_MASK GENMASK(7, 2)
|
||||
+
|
||||
+#define PHY_PARAM_CTRL1_MASK \
|
||||
+ (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
|
||||
+ PHY_PARAM_CTRL1_LOS_BIAS_MASK)
|
||||
+
|
||||
+#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
|
||||
+ (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
|
||||
+ (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
|
||||
+ (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
|
||||
+#define PHY_PARAM_CTRL1_LOS_BIAS(x) \
|
||||
+ (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
|
||||
+
|
||||
+/* RX OVRD IN HI bits */
|
||||
+#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
|
||||
+#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_MASK GENMASK(10, 7)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ(x) ((x) << 8)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
|
||||
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
|
||||
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK GENMASK(4, 2)
|
||||
+#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
|
||||
+#define RX_OVRD_IN_HI_RX_RATE_MASK GENMASK(2, 0)
|
||||
+
|
||||
+/* TX OVRD DRV LO register bits */
|
||||
+#define TX_OVRD_DRV_LO_AMPLITUDE_MASK GENMASK(6, 0)
|
||||
+#define TX_OVRD_DRV_LO_PREEMPH_MASK GENMASK(13, 6)
|
||||
+#define TX_OVRD_DRV_LO_PREEMPH(x) ((x) << 7)
|
||||
+#define TX_OVRD_DRV_LO_EN BIT(14)
|
||||
+
|
||||
+/* MPLL bits */
|
||||
+#define SSPHY_MPLL_MASK GENMASK(8, 5)
|
||||
+#define SSPHY_MPLL(x) ((x) << 5)
|
||||
+
|
||||
+/* SS CAP register bits */
|
||||
+#define SS_CR_CAP_ADDR_REG BIT(0)
|
||||
+#define SS_CR_CAP_DATA_REG BIT(0)
|
||||
+#define SS_CR_READ_REG BIT(0)
|
||||
+#define SS_CR_WRITE_REG BIT(0)
|
||||
+
|
||||
+struct usb_phy {
|
||||
+ void __iomem *base;
|
||||
+ struct device *dev;
|
||||
+ struct clk *xo_clk;
|
||||
+ struct clk *ref_clk;
|
||||
+ u32 rx_eq;
|
||||
+ u32 tx_deamp_3_5db;
|
||||
+ u32 mpll;
|
||||
+};
|
||||
+
|
||||
+struct phy_drvdata {
|
||||
+ struct phy_ops ops;
|
||||
+ u32 clk_rate;
|
||||
+};
|
||||
+
|
||||
+/**
|
||||
+ * Write register and read back masked value to confirm it is written
|
||||
+ *
|
||||
+ * @base - QCOM DWC3 PHY base virtual address.
|
||||
+ * @offset - register offset.
|
||||
+ * @mask - register bitmask specifying what should be updated
|
||||
+ * @val - value to write.
|
||||
+ */
|
||||
+static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
|
||||
+ u32 offset,
|
||||
+ const u32 mask, u32 val)
|
||||
+{
|
||||
+ u32 write_val, tmp = readl(phy_dwc3->base + offset);
|
||||
+
|
||||
+ tmp &= ~mask; /* retain other bits */
|
||||
+ write_val = tmp | val;
|
||||
+
|
||||
+ writel(write_val, phy_dwc3->base + offset);
|
||||
+
|
||||
+ /* Read back to see if val was written */
|
||||
+ tmp = readl(phy_dwc3->base + offset);
|
||||
+ tmp &= mask; /* clear other bits */
|
||||
+
|
||||
+ if (tmp != val)
|
||||
+ dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
|
||||
+}
|
||||
+
|
||||
+static int wait_for_latch(void __iomem *addr)
|
||||
+{
|
||||
+ u32 retry = 10;
|
||||
+
|
||||
+ while (true) {
|
||||
+ if (!readl(addr))
|
||||
+ break;
|
||||
+
|
||||
+ if (--retry == 0)
|
||||
+ return -ETIMEDOUT;
|
||||
+
|
||||
+ usleep_range(10, 20);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * Write SSPHY register
|
||||
+ *
|
||||
+ * @base - QCOM DWC3 PHY base virtual address.
|
||||
+ * @addr - SSPHY address to write.
|
||||
+ * @val - value to write.
|
||||
+ */
|
||||
+static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
|
||||
+ u32 addr, u32 val)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
|
||||
+ writel(SS_CR_CAP_ADDR_REG,
|
||||
+ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
|
||||
+ writel(SS_CR_CAP_DATA_REG,
|
||||
+ phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
|
||||
+
|
||||
+err_wait:
|
||||
+ if (ret)
|
||||
+ dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * Read SSPHY register.
|
||||
+ *
|
||||
+ * @base - QCOM DWC3 PHY base virtual address.
|
||||
+ * @addr - SSPHY address to read.
|
||||
+ */
|
||||
+static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
|
||||
+ u32 addr, u32 *val)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
|
||||
+ writel(SS_CR_CAP_ADDR_REG,
|
||||
+ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ /*
|
||||
+ * Due to hardware bug, first read of SSPHY register might be
|
||||
+ * incorrect. Hence as workaround, SW should perform SSPHY register
|
||||
+ * read twice, but use only second read and ignore first read.
|
||||
+ */
|
||||
+ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ /* throwaway read */
|
||||
+ readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
|
||||
+
|
||||
+ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
|
||||
+
|
||||
+err_wait:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+ u32 val;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
|
||||
+ * enable clamping, and disable RETENTION (power-on default is ENABLED)
|
||||
+ */
|
||||
+ val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
|
||||
+ HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
|
||||
+ HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
|
||||
+ HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
|
||||
+ HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
|
||||
+
|
||||
+ /* use core clock if external reference is not present */
|
||||
+ if (!phy_dwc3->xo_clk)
|
||||
+ val |= HSUSB_CTRL_USE_CLKCORE;
|
||||
+
|
||||
+ writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
|
||||
+ usleep_range(2000, 2200);
|
||||
+
|
||||
+ /* Disable (bypass) VBUS and ID filters */
|
||||
+ writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_disable_unprepare(phy_dwc3->ref_clk);
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+ u32 data;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* reset phy */
|
||||
+ data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+ writel(data | SSUSB_CTRL_SS_PHY_RESET,
|
||||
+ phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+ usleep_range(2000, 2200);
|
||||
+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+
|
||||
+ /* clear REF_PAD if we don't have XO clk */
|
||||
+ if (!phy_dwc3->xo_clk)
|
||||
+ data &= ~SSUSB_CTRL_REF_USE_PAD;
|
||||
+ else
|
||||
+ data |= SSUSB_CTRL_REF_USE_PAD;
|
||||
+
|
||||
+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+
|
||||
+ /* wait for ref clk to become stable, this can take up to 30ms */
|
||||
+ msleep(30);
|
||||
+
|
||||
+ data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
|
||||
+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+
|
||||
+ /*
|
||||
+ * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
|
||||
+ * in HS mode instead of SS mode. Workaround it by asserting
|
||||
+ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
|
||||
+ */
|
||||
+ ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data |= (1 << 7);
|
||||
+ ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~0xff0;
|
||||
+ data |= 0x20;
|
||||
+ ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ /*
|
||||
+ * Fix RX Equalization setting as follows
|
||||
+ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
|
||||
+ */
|
||||
+ ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
|
||||
+ data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
|
||||
+ ret = usb_ss_write_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ /*
|
||||
+ * Set EQ and TX launch amplitudes as follows
|
||||
+ * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
|
||||
+ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
|
||||
+ * LANE0.TX_OVRD_DRV_LO.EN set to 1.
|
||||
+ */
|
||||
+ ret = usb_ss_read_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
|
||||
+ data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
|
||||
+ data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
|
||||
+ data |= 0x6E;
|
||||
+ data |= TX_OVRD_DRV_LO_EN;
|
||||
+ ret = usb_ss_write_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data = 0;
|
||||
+ data &= ~SSPHY_MPLL_MASK;
|
||||
+ data |= SSPHY_MPLL(phy_dwc3->mpll);
|
||||
+ usb_ss_write_phycreg(phy_dwc3, 0x30, data);
|
||||
+
|
||||
+ /*
|
||||
+ * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
|
||||
+ * TX_FULL_SWING [26:20] amplitude to 110
|
||||
+ * TX_DEEMPH_6DB [19:14] to 32
|
||||
+ * TX_DEEMPH_3_5DB [13:8] set based on SoC version
|
||||
+ * LOS_BIAS [7:3] to 9
|
||||
+ */
|
||||
+ data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
|
||||
+
|
||||
+ data &= ~PHY_PARAM_CTRL1_MASK;
|
||||
+
|
||||
+ data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
|
||||
+ PHY_PARAM_CTRL1_LOS_BIAS(0x9);
|
||||
+
|
||||
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
|
||||
+ PHY_PARAM_CTRL1_MASK, data);
|
||||
+
|
||||
+err_phy_trans:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+
|
||||
+ /* Sequence to put SSPHY in low power state:
|
||||
+ * 1. Clear REF_PHY_EN in PHY_CTRL_REG
|
||||
+ * 2. Clear REF_USE_PAD in PHY_CTRL_REG
|
||||
+ * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
|
||||
+ */
|
||||
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_SS_PHY_EN, 0x0);
|
||||
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_REF_USE_PAD, 0x0);
|
||||
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_TEST_POWERDOWN, 0x0);
|
||||
+
|
||||
+ clk_disable_unprepare(phy_dwc3->ref_clk);
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = {
|
||||
+ .ops = {
|
||||
+ .init = qcom_ipq806x_usb_hs_phy_init,
|
||||
+ .exit = qcom_ipq806x_usb_hs_phy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+ .clk_rate = 60000000,
|
||||
+};
|
||||
+
|
||||
+static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = {
|
||||
+ .ops = {
|
||||
+ .init = qcom_ipq806x_usb_ss_phy_init,
|
||||
+ .exit = qcom_ipq806x_usb_ss_phy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+ .clk_rate = 125000000,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id qcom_ipq806x_usb_phy_table[] = {
|
||||
+ { .compatible = "qcom,ipq806x-usb-phy-hs",
|
||||
+ .data = &qcom_ipq806x_usb_hs_drvdata },
|
||||
+ { .compatible = "qcom,ipq806x-usb-phy-ss",
|
||||
+ .data = &qcom_ipq806x_usb_ss_drvdata },
|
||||
+ { /* Sentinel */ }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table);
|
||||
+
|
||||
+static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res;
|
||||
+ resource_size_t size;
|
||||
+ struct phy *generic_phy;
|
||||
+ struct usb_phy *phy_dwc3;
|
||||
+ const struct phy_drvdata *data;
|
||||
+ struct phy_provider *phy_provider;
|
||||
+
|
||||
+ phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
|
||||
+ if (!phy_dwc3)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ data = of_device_get_match_data(&pdev->dev);
|
||||
+
|
||||
+ phy_dwc3->dev = &pdev->dev;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ if (!res)
|
||||
+ return -EINVAL;
|
||||
+ size = resource_size(res);
|
||||
+ phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
|
||||
+
|
||||
+ if (IS_ERR(phy_dwc3->base)) {
|
||||
+ dev_err(phy_dwc3->dev, "failed to map reg\n");
|
||||
+ return PTR_ERR(phy_dwc3->base);
|
||||
+ }
|
||||
+
|
||||
+ phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
|
||||
+ if (IS_ERR(phy_dwc3->ref_clk)) {
|
||||
+ dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
|
||||
+ return PTR_ERR(phy_dwc3->ref_clk);
|
||||
+ }
|
||||
+
|
||||
+ clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
|
||||
+
|
||||
+ phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
|
||||
+ if (IS_ERR(phy_dwc3->xo_clk)) {
|
||||
+ dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
|
||||
+ phy_dwc3->xo_clk = NULL;
|
||||
+ }
|
||||
+
|
||||
+ /* Parse device node to probe HSIO settings */
|
||||
+ if (device_property_read_u32(&pdev->dev, "qcom,rx-eq",
|
||||
+ &phy_dwc3->rx_eq))
|
||||
+ phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
|
||||
+
|
||||
+ if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
|
||||
+ &phy_dwc3->tx_deamp_3_5db))
|
||||
+ phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
|
||||
+
|
||||
+ if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
|
||||
+ phy_dwc3->mpll = SSPHY_MPLL_VALUE;
|
||||
+
|
||||
+ generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
|
||||
+
|
||||
+ if (IS_ERR(generic_phy))
|
||||
+ return PTR_ERR(generic_phy);
|
||||
+
|
||||
+ phy_set_drvdata(generic_phy, phy_dwc3);
|
||||
+ platform_set_drvdata(pdev, phy_dwc3);
|
||||
+
|
||||
+ phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
|
||||
+ of_phy_simple_xlate);
|
||||
+
|
||||
+ if (IS_ERR(phy_provider))
|
||||
+ return PTR_ERR(phy_provider);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver qcom_ipq806x_usb_phy_driver = {
|
||||
+ .probe = qcom_ipq806x_usb_phy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "qcom-ipq806x-usb-phy",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = qcom_ipq806x_usb_phy_table,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(qcom_ipq806x_usb_phy_driver);
|
||||
+
|
||||
+MODULE_ALIAS("platform:phy-qcom-ipq806x-usb");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
|
||||
+MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
|
||||
+MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");
|
||||
@ -0,0 +1,31 @@
|
||||
From 3d7b0ca5300bd01b176f2b4c10e173db802560d8 Mon Sep 17 00:00:00 2001
|
||||
From: Colin Ian King <colin.king@canonical.com>
|
||||
Date: Tue, 21 Jul 2020 16:06:13 +0100
|
||||
Subject: phy: qualcomm: fix setting of tx_deamp_3_5db when device property
|
||||
read fails
|
||||
|
||||
Currently when reading of the device property for "qcom,tx-deamp_3_5db"
|
||||
fails the default is being assigned incorrectly to phy_dwc3->rx_eq. This
|
||||
looks like a copy-n-paste error and in fact should be assigning the
|
||||
default instead to phy_dwc3->tx_deamp_3_5db
|
||||
|
||||
Addresses-Coverity: ("Copy-paste error")
|
||||
Fixes: ef19b117b834 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver")
|
||||
Signed-off-by: Colin Ian King <colin.king@canonical.com>
|
||||
Link: https://lore.kernel.org/r/20200721150613.416876-1-colin.king@canonical.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
|
||||
+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
|
||||
@@ -531,7 +531,7 @@ static int qcom_ipq806x_usb_phy_probe(st
|
||||
|
||||
if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
|
||||
&phy_dwc3->tx_deamp_3_5db))
|
||||
- phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
|
||||
+ phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
|
||||
|
||||
if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
|
||||
phy_dwc3->mpll = SSPHY_MPLL_VALUE;
|
||||
Loading…
Reference in New Issue
Block a user