Openwrt/openwrt/target/linux/brcm63xx-2.6/patches/000-arch_mips.patch

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--- linux-2.6.17/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
+++ linux-2.6.17-brcm63xx/arch/mips/Kconfig 2006-07-13 19:08:11.000000000 +0200
@@ -12,6 +12,15 @@
prompt "System type"
default SGI_IP22
+config MIPS_BRCM
+ bool "Support for the Broadcom boards"
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_HAS_CPU_MIPS32_R1
+ select IRQ_CPU
+ help
+ This is a fmaily of boards based on the Broadcom MIPS32
+
config MIPS_MTX1
bool "4G Systems MTX-1 board"
select DMA_NONCOHERENT
@@ -780,6 +789,7 @@
endchoice
+source "arch/mips/brcm-boards/bcm963xx/Kconfig"
source "arch/mips/ddb5xxx/Kconfig"
source "arch/mips/gt64120/ev64120/Kconfig"
source "arch/mips/jazz/Kconfig"
--- linux-2.6.17/arch/mips/Makefile 2006-06-18 03:49:35.000000000 +0200
+++ linux-2.6.17-brcm63xx/arch/mips/Makefile 2006-07-13 18:55:59.000000000 +0200
@@ -145,6 +145,20 @@
#
#
+# Broadcom board
+#
+core-$(CONFIG_MIPS_BRCM) += arch/mips/brcm-boards/generic/ arch/mips/brcm-boards/bcm963xx/
+core-$(CONFIG_MIPS_BRCM) += bcmdrivers/opensource/char/serial/impl1/
+#core-$(CONFIG_MIPS_BRCM) += bcmdrivers/opensource/char/board/bcm963xx/impl1/
+#core-$(CONFIG_MIPS_BRCM) += boardparms/bcm963xx/
+cflags-$(CONFIG_MIPS_BRCM) += -Iinclude/asm-mips/mach-bcm963xx
+cflags-$(CONFIG_MIPS_BRCM) += -Iarch/mips/brcm-boards/generic/include
+cflags-$(CONFIG_MIPS_BRCM) += -Ibcmdrivers/opensource/include/bcm963xx
+cflags-$(CONFIG_MIPS_BRCM) += -Iboardparms/bcm963xx
+load-$(CONFIG_MIPS_BRCM) += 0xffffffff80010000
+
+
+#
# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
#
core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
diff -urN linux-2.6.17/arch/mips/kernel/cpu-probe.c linux-2.6.17-brcm63xx/arch/mips/kernel/cpu-probe.c
--- linux-2.6.17/arch/mips/kernel/cpu-probe.c 2006-06-18 03:49:35.000000000 +0200
+++ linux-2.6.17-brcm63xx/arch/mips/kernel/cpu-probe.c 2006-07-13 18:59:04.000000000 +0200
@@ -568,6 +568,25 @@
return;
}
+static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
+{
+ decode_configs(c);
+ switch (c->processor_id & 0xff00) {
+ case PRID_IMP_BCM6338:
+ c->cputype = CPU_BCM6338;
+ break;
+ case PRID_IMP_BCM6345:
+ c->cputype = CPU_BCM6345;
+ break;
+ case PRID_IMP_BCM6348:
+ c->cputype = CPU_BCM6348;
+ break;
+ default:
+ c->cputype = CPU_UNKNOWN;
+ break;
+ }
+}
+
static inline void cpu_probe_mips(struct cpuinfo_mips *c)
{
decode_configs(c);
@@ -704,6 +723,9 @@
case PRID_COMP_LEGACY:
cpu_probe_legacy(c);
break;
+ case PRID_COMP_BROADCOM:
+ cpu_probe_broadcom(c);
+ break;
case PRID_COMP_MIPS:
cpu_probe_mips(c);
break;
diff -urN linux-2.6.17/arch/mips/kernel/proc.c linux-2.6.17-brcm63xx/arch/mips/kernel/proc.c
--- linux-2.6.17/arch/mips/kernel/proc.c 2006-06-18 03:49:35.000000000 +0200
+++ linux-2.6.17-brcm63xx/arch/mips/kernel/proc.c 2006-07-13 19:00:53.000000000 +0200
@@ -85,6 +85,9 @@
[CPU_VR4181A] = "NEC VR4181A",
[CPU_SR71000] = "Sandcraft SR71000",
[CPU_PR4450] = "Philips PR4450",
+ [CPU_BCM6338] = "BCM6338",
+ [CPU_BCM6345] = "BCM6345",
+ [CPU_BCM6348] = "BCM6348",
};
diff -urN linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-brcm63xx/arch/mips/mm/c-r4k.c
--- linux-2.6.17/arch/mips/mm/c-r4k.c 2006-06-18 03:49:35.000000000 +0200
+++ linux-2.6.17-brcm63xx/arch/mips/mm/c-r4k.c 2006-07-13 19:03:23.000000000 +0200
@@ -914,6 +914,13 @@
if (!(config & MIPS_CONF_M))
panic("Don't know how to probe P-caches on this cpu.");
+ if (c->cputype == CPU_BCM6338 || c->cputype == CPU_BCM6345 || c->cputype == CPU_BCM6348)
+ {
+ printk("brcm mips: enabling icache and dcache...\n");
+ /* Enable caches */
+ write_c0_diag(read_c0_diag() | 0xC0000000);
+ }
+
/*
* So we seem to be a MIPS32 or MIPS64 CPU
* So let's probe the I-cache ...
diff -urN linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-brcm63xx/arch/mips/mm/tlbex.c
--- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
+++ linux-2.6.17-brcm63xx/arch/mips/mm/tlbex.c 2006-07-13 19:03:57.000000000 +0200
@@ -882,6 +882,9 @@
case CPU_4KSC:
case CPU_20KC:
case CPU_25KF:
+ case CPU_BCM6338:
+ case CPU_BCM6345:
+ case CPU_BCM6348:
tlbw(p);
break;