2020-04-19 08:04:06 +00:00
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From 5c74c54ce6fff719999ff48f128cf4150ee4ff59 Mon Sep 17 00:00:00 2001
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From: Iwan R Timmer <irtimmer@gmail.com>
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Date: Thu, 7 Nov 2019 22:11:13 +0100
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Subject: [PATCH] net: dsa: mv88e6xxx: Split monitor port configuration
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Separate the configuration of the egress and ingress monitor port.
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This allows the port mirror functionality to do ingress and egress
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port mirroring to separate ports.
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Signed-off-by: Iwan R Timmer <irtimmer@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/mv88e6xxx/chip.c | 9 ++++++-
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drivers/net/dsa/mv88e6xxx/chip.h | 9 ++++++-
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drivers/net/dsa/mv88e6xxx/global1.c | 42 ++++++++++++++++++++---------
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drivers/net/dsa/mv88e6xxx/global1.h | 8 ++++--
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4 files changed, 52 insertions(+), 16 deletions(-)
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--- a/drivers/net/dsa/mv88e6xxx/chip.c
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+++ b/drivers/net/dsa/mv88e6xxx/chip.c
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2021-02-10 16:20:24 +00:00
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@@ -2384,7 +2384,14 @@ static int mv88e6xxx_setup_upstream_port
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2020-04-19 08:04:06 +00:00
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if (chip->info->ops->set_egress_port) {
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err = chip->info->ops->set_egress_port(chip,
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- upstream_port);
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+ MV88E6XXX_EGRESS_DIR_INGRESS,
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+ upstream_port);
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+ if (err)
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+ return err;
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+
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+ err = chip->info->ops->set_egress_port(chip,
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+ MV88E6XXX_EGRESS_DIR_EGRESS,
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+ upstream_port);
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if (err)
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return err;
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}
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--- a/drivers/net/dsa/mv88e6xxx/chip.h
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+++ b/drivers/net/dsa/mv88e6xxx/chip.h
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@@ -33,6 +33,11 @@ enum mv88e6xxx_egress_mode {
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MV88E6XXX_EGRESS_MODE_ETHERTYPE,
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};
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+enum mv88e6xxx_egress_direction {
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+ MV88E6XXX_EGRESS_DIR_INGRESS,
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+ MV88E6XXX_EGRESS_DIR_EGRESS,
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+};
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+
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enum mv88e6xxx_frame_mode {
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MV88E6XXX_FRAME_MODE_NORMAL,
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MV88E6XXX_FRAME_MODE_DSA,
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@@ -464,7 +469,9 @@ struct mv88e6xxx_ops {
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int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
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uint64_t *data);
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int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
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- int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
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+ int (*set_egress_port)(struct mv88e6xxx_chip *chip,
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+ enum mv88e6xxx_egress_direction direction,
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+ int port);
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#define MV88E6XXX_CASCADE_PORT_NONE 0xe
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#define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
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--- a/drivers/net/dsa/mv88e6xxx/global1.c
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+++ b/drivers/net/dsa/mv88e6xxx/global1.c
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2020-12-02 11:45:04 +00:00
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@@ -294,7 +294,9 @@ int mv88e6250_g1_ieee_pri_map(struct mv8
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2020-04-19 08:04:06 +00:00
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/* Offset 0x1a: Monitor Control */
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/* Offset 0x1a: Monitor & MGMT Control on some devices */
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-int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
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+int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
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+ enum mv88e6xxx_egress_direction direction,
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+ int port)
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{
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u16 reg;
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int err;
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2020-12-02 11:45:04 +00:00
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@@ -303,11 +305,20 @@ int mv88e6095_g1_set_egress_port(struct
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2020-04-19 08:04:06 +00:00
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if (err)
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return err;
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- reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
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- MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
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-
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- reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
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- port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
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+ switch (direction) {
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+ case MV88E6XXX_EGRESS_DIR_INGRESS:
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+ reg &= MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
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+ reg |= port <<
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+ __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
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+ break;
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+ case MV88E6XXX_EGRESS_DIR_EGRESS:
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+ reg &= MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
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+ reg |= port <<
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+ __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
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}
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2020-12-02 11:45:04 +00:00
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@@ -341,17 +352,24 @@ static int mv88e6390_g1_monitor_write(st
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2020-04-19 08:04:06 +00:00
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return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
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}
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-int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
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+int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
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+ enum mv88e6xxx_egress_direction direction,
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+ int port)
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{
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u16 ptr;
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int err;
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- ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
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- err = mv88e6390_g1_monitor_write(chip, ptr, port);
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- if (err)
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- return err;
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+ switch (direction) {
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+ case MV88E6XXX_EGRESS_DIR_INGRESS:
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+ ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
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+ break;
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+ case MV88E6XXX_EGRESS_DIR_EGRESS:
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+ ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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- ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
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err = mv88e6390_g1_monitor_write(chip, ptr, port);
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if (err)
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return err;
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--- a/drivers/net/dsa/mv88e6xxx/global1.h
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+++ b/drivers/net/dsa/mv88e6xxx/global1.h
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2020-12-02 11:45:04 +00:00
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@@ -289,8 +289,12 @@ int mv88e6095_g1_stats_set_histogram(str
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2020-04-19 08:04:06 +00:00
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int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
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void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
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int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
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-int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
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-int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
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+int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
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+ enum mv88e6xxx_egress_direction direction,
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+ int port);
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+int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
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+ enum mv88e6xxx_egress_direction direction,
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+ int port);
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int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
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int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
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int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
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