Openwrt/target/linux/imx6/patches-5.10/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch

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From b6764bb27c819cdcf854371db485a43d71f579f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
Date: Tue, 3 Mar 2020 15:15:57 +0100
Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: make switch3 reset button
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Petr Štetiar <ynezz@true.cz>
---
arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 15 ++++++++++++++-
arch/arm/boot/dts/imx6q-apalis-ixora.dts | 15 ++++++++++++++-
2 files changed, 28 insertions(+), 2 deletions(-)
--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -38,7 +38,7 @@
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
+ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
wakeup {
label = "Wake-Up";
@@ -47,6 +47,13 @@
debounce-interval = <10>;
wakeup-source;
};
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <10>;
+ };
};
lcd_display: disp0 {
@@ -275,4 +282,10 @@
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
>;
};
+
+ pinctrl_switch3_ixora: switch3ixora {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
+ >;
+ };
};
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -37,7 +37,7 @@
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
+ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
wakeup {
label = "Wake-Up";
@@ -46,6 +46,13 @@
debounce-interval = <10>;
wakeup-source;
};
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <10>;
+ };
};
lcd_display: disp0 {
@@ -276,4 +283,10 @@
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
>;
};
+
+ pinctrl_switch3_ixora: switch3ixora {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
+ >;
+ };
};