55 lines
2.2 KiB
Diff
55 lines
2.2 KiB
Diff
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From 3b0f26629fef1b55a71031b4ef4db27d0a66a0be Mon Sep 17 00:00:00 2001
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From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Date: Wed, 29 May 2013 21:32:47 +0200
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Subject: [PATCH 22/29] net: mv643xx_eth: proper initialization for Kirkwood
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SoCs
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Ethernet controllers found on Kirkwood SoCs not only suffer from loosing
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MAC address register contents on clock gating but also some important
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registers are reset to values that would break ethernet. This patch
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clears the CLK125_BYPASS_EN bit for DT enabled Kirkwood only by using
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of_device_is_compatible() instead of #ifdefs. Non-DT Kirkwood is not
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affected as it installs a clock gating workaround because of the MAC
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address issue above. Other Orion SoCs do not suffer from register reset,
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do not have the bit in question, or do not have the register at all.
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Moreover, system controllers on PPC using this driver should also be
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protected from clearing that bit.
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Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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---
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drivers/net/ethernet/marvell/mv643xx_eth.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
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index 946033b..af6bdcc 100644
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--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
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+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
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@@ -116,6 +116,8 @@ static char mv643xx_eth_driver_version[] = "1.4";
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#define LINK_UP 0x00000002
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#define TXQ_COMMAND 0x0048
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#define TXQ_FIX_PRIO_CONF 0x004c
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+#define PORT_SERIAL_CONTROL1 0x004c
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+#define CLK125_BYPASS_EN 0x00000010
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#define TX_BW_RATE 0x0050
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#define TX_BW_MTU 0x0058
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#define TX_BW_BURST 0x005c
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@@ -2701,6 +2703,15 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
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mp->dev = dev;
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+ /* Kirkwood resets some registers on gated clocks. Especially
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+ * CLK125_BYPASS_EN must be cleared but is not available on
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+ * all other SoCs/System Controllers using this driver.
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+ */
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+ if (of_device_is_compatible(pdev->dev.of_node,
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+ "marvell,kirkwood-eth-port"))
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+ wrlp(mp, PORT_SERIAL_CONTROL1,
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+ rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
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+
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/*
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* Start with a default rate, and if there is a clock, allow
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* it to override the default.
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--
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1.8.4.rc1
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