2007-06-02 23:13:51 +00:00
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/*
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2007-07-11 13:00:27 +00:00
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* $Id$
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*
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2007-06-02 23:13:51 +00:00
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* ADM5120 interrupt controller definitions
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*
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* This header file defines the hardware registers of the ADM5120 SoC
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* built-in interrupt controller.
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*
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* Copyright (C) 2007 OpenWrt.org
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2007-08-29 17:27:11 +00:00
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* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
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2007-06-02 23:13:51 +00:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*/
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2007-07-11 13:00:27 +00:00
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2007-06-02 23:13:51 +00:00
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#ifndef _ADM5120_INTC_H_
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#define _ADM5120_INTC_H_
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/*
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* INTC register offsets
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*/
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#define INTC_REG_IRQ_STATUS 0x00 /* Interrupt status after masking */
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#define INTC_REG_IRQ_RAW_STATUS 0x04 /* Interrupt status before masking */
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#define INTC_REG_IRQ_ENABLE 0x08 /* Used to enable the interrupt sources */
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#define INTC_REG_IRQ_ENABLE_CLEAR 0x0C /* Used to disable the interrupt sources */
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#define INTC_REG_IRQ_DISABLE INTC_REG_IRQ_ENABLE_CLEAR
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#define INTC_REG_INT_MODE 0x14 /* The interrupt mode of the sources */
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#define INTC_REG_FIQ_STATUS 0x18 /* FIQ status */
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#define INTC_REG_IRQ_TEST_SOURCE 0x1C
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#define INTC_REG_IRQ_SOURCE_SELECT 0x20
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#define INTC_REG_INT_LEVEL 0x24
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/*
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* INTC IRQ numbers
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*/
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#define INTC_IRQ_TIMER 0 /* built in timer */
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#define INTC_IRQ_UART0 1 /* built-in UART0 */
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#define INTC_IRQ_UART1 2 /* built-in UART1 */
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#define INTC_IRQ_USBC 3 /* USB Host Controller */
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#define INTC_IRQ_GPIO2 4 /* GPIO line 2 */
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#define INTC_IRQ_GPIO4 5 /* GPIO line 4 */
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#define INTC_IRQ_PCI0 6 /* PCI slot 2 */
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#define INTC_IRQ_PCI1 7 /* PCI slot 3 */
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#define INTC_IRQ_PCI2 8 /* PCI slot 4 */
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#define INTC_IRQ_SWITCH 9 /* built-in ethernet switch */
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#define INTC_IRQ_LAST INTC_IRQ_SWITCH
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#define INTC_IRQ_COUNT 10
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/*
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* INTC register bits
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*/
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#define INTC_INT_TIMER ( 1 << INTC_IRQ_TIMER )
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#define INTC_INT_UART0 ( 1 << INTC_IRQ_UART0 )
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#define INTC_INT_UART1 ( 1 << INTC_IRQ_UART1 )
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#define INTC_INT_USBC ( 1 << INTC_IRQ_USBC )
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#define INTC_INT_INTX0 ( 1 << INTC_IRQ_INTX0 )
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#define INTC_INT_INTX1 ( 1 << INTC_IRQ_INTX1 )
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#define INTC_INT_PCI0 ( 1 << INTC_IRQ_PCI0 )
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#define INTC_INT_PCI1 ( 1 << INTC_IRQ_PCI1 )
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#define INTC_INT_PCI2 ( 1 << INTC_IRQ_PCI2 )
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#define INTC_INT_SWITCH ( 1 << INTC_IRQ_SWITCH )
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#define INTC_INT_ALL (( 1 << INTC_IRQ_COUNT)-1)
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#endif /* _ADM5120_INTC_H_ */
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