89 lines
2.9 KiB
Diff
89 lines
2.9 KiB
Diff
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From acb69c6600c3df52f0b3610801f3fd44c4392333 Mon Sep 17 00:00:00 2001
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Message-Id: <acb69c6600c3df52f0b3610801f3fd44c4392333.1559210220.git.ryder.lee@mediatek.com>
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From: Ryder Lee <ryder.lee@mediatek.com>
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Date: Wed, 13 Mar 2019 16:42:15 +0800
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Subject: [PATCH] arm: dts: mediatek: add basic support for MT7629 SoC
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This adds basic support for MT7629 reference board.
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Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
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---
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include/dt-bindings/reset/mt7629-resets.h | 71 ++++
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4 files changed, 704 insertions(+)
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create mode 100644 include/dt-bindings/reset/mt7629-resets.h
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--- /dev/null
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+++ b/include/dt-bindings/reset/mt7629-resets.h
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@@ -0,0 +1,71 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * Copyright (C) 2019 MediaTek Inc.
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+ */
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+
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+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
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+#define _DT_BINDINGS_RESET_CONTROLLER_MT7629
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+
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+/* INFRACFG resets */
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+#define MT7629_INFRA_EMI_MPU_RST 0
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+#define MT7629_INFRA_UART5_RST 2
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+#define MT7629_INFRA_CIRQ_EINT_RST 3
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+#define MT7629_INFRA_APXGPT_RST 4
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+#define MT7629_INFRA_SCPSYS_RST 5
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+#define MT7629_INFRA_KP_RST 6
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+#define MT7629_INFRA_SPI1_RST 7
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+#define MT7629_INFRA_SPI4_RST 8
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+#define MT7629_INFRA_SYSTIMER_RST 9
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+#define MT7629_INFRA_IRRX_RST 10
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+#define MT7629_INFRA_AO_BUS_RST 16
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+#define MT7629_INFRA_EMI_RST 32
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+#define MT7629_INFRA_APMIXED_RST 35
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+#define MT7629_INFRA_MIPI_RST 36
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+#define MT7629_INFRA_TRNG_RST 37
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+#define MT7629_INFRA_SYSCIRQ_RST 38
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+#define MT7629_INFRA_MIPI_CSI_RST 39
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+#define MT7629_INFRA_GCE_FAXI_RST 40
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+#define MT7629_INFRA_I2C_SRAM_RST 41
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+#define MT7629_INFRA_IOMMU_RST 47
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+
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+/* PERICFG resets */
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+#define MT7629_PERI_UART0_SW_RST 0
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+#define MT7629_PERI_UART1_SW_RST 1
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+#define MT7629_PERI_UART2_SW_RST 2
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+#define MT7629_PERI_BTIF_SW_RST 6
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+#define MT7629_PERI_PWN_SW_RST 8
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+#define MT7629_PERI_DMA_SW_RST 11
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+#define MT7629_PERI_NFI_SW_RST 14
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+#define MT7629_PERI_I2C0_SW_RST 22
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+#define MT7629_PERI_SPI0_SW_RST 33
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+#define MT7629_PERI_SPI1_SW_RST 34
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+#define MT7629_PERI_FLASHIF_SW_RST 36
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+
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+/* PCIe Subsystem resets */
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+#define MT7629_PCIE1_CORE_RST 19
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+#define MT7629_PCIE1_MMIO_RST 20
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+#define MT7629_PCIE1_HRST 21
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+#define MT7629_PCIE1_USER_RST 22
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+#define MT7629_PCIE1_PIPE_RST 23
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+#define MT7629_PCIE0_CORE_RST 27
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+#define MT7629_PCIE0_MMIO_RST 28
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+#define MT7629_PCIE0_HRST 29
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+#define MT7629_PCIE0_USER_RST 30
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+#define MT7629_PCIE0_PIPE_RST 31
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+
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+/* SSUSB Subsystem resets */
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+#define MT7629_SSUSB_PHY_PWR_RST 3
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+#define MT7629_SSUSB_MAC_PWR_RST 4
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+
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+/* ETH Subsystem resets */
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+#define MT7629_ETHSYS_SYS_RST 0
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+#define MT7629_ETHSYS_MCM_RST 2
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+#define MT7629_ETHSYS_HSDMA_RST 5
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+#define MT7629_ETHSYS_FE_RST 6
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+#define MT7629_ETHSYS_ESW_RST 16
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+#define MT7629_ETHSYS_GMAC_RST 23
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+#define MT7629_ETHSYS_EPHY_RST 24
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+#define MT7629_ETHSYS_CRYPTO_RST 29
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+#define MT7629_ETHSYS_PPE_RST 31
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+
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+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */
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