67 lines
2.6 KiB
C
67 lines
2.6 KiB
C
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2005 infineon
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*/
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#ifndef _DANUBE_IRQ__
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#define _DANUBE_IRQ__
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#define INT_NUM_IRQ0 8
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#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
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#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
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#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
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#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
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#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
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#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
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#define DANUBEASC1_TIR (INT_NUM_IM3_IRL0 + 7)
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#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9)
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#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10)
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#define DANUBE_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
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#define DANUBE_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
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#define DANUBE_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
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#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
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#define MIPS_CPU_TIMER_IRQ 7
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#define DANUBE_DMA_CH0_INT (INT_NUM_IM2_IRL0)
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#define DANUBE_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
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#define DANUBE_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
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#define DANUBE_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
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#define DANUBE_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
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#define DANUBE_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
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#define DANUBE_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
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#define DANUBE_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
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#define DANUBE_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
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#define DANUBE_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
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#define DANUBE_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
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#define DANUBE_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
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#define DANUBE_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
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#define DANUBE_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
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#define DANUBE_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
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#define DANUBE_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
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#define DANUBE_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
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#define DANUBE_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
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#define DANUBE_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
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#define DANUBE_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
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extern void mask_and_ack_danube_irq (unsigned int irq_nr);
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#endif
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