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Openwrt/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch

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mediatek: enable coherent DMA for ethernet and PCI Improves performance by eliminating the need for extra cache flushes Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-09-04 17:41:46 +00:00
From: Felix Fietkau <nbd@nbd.name>
Date: Fri, 4 Sep 2020 18:36:06 +0200
Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for coherent DMA
It improves performance by eliminating the need for a cache flush on rx and tx
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -357,7 +357,7 @@
};
cci_control2: slave-if@5000 {
- compatible = "arm,cci-400-ctrl-if";
+ compatible = "arm,cci-400-ctrl-if", "syscon";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
kernel-5.4: bump to 5.4.102 and refresh patches 5.4.102 backported a lot of stuff that our WireGuard backport already did, in addition to other patches we had, so those patches were removed from that part of the series. In the process other patches were refreshed or reworked to account for upstream changes. This commit involved `update_kernel.sh -v -u 5.4`. Cc: John Audia <graysky@archlinux.us> Cc: David Bauer <mail@david-bauer.net> Cc: Petr Štetiar <ynezz@true.cz> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
2021-03-04 20:37:13 +00:00
@@ -969,6 +969,8 @@
mediatek: enable coherent DMA for ethernet and PCI Improves performance by eliminating the need for extra cache flushes Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-09-04 17:41:46 +00:00
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys>;
+ mediatek,cci-control = <&cci_control2>;
+ dma-coherent;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -9,6 +9,7 @@
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
+#include <linux/of_address.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/clk.h>
kernel: improve skb hash on the mtk ethernet driver The PPE only provides a 14 bit hash, however many uses of the skb hash expect the hash to use the full 32 bit range. Use jhash to extend the hash to the full size Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-12-18 16:10:04 +00:00
@@ -2485,6 +2486,13 @@ static int mtk_hw_init(struct mtk_eth *e
mediatek: enable coherent DMA for ethernet and PCI Improves performance by eliminating the need for extra cache flushes Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-09-04 17:41:46 +00:00
if (ret)
goto err_disable_pm;
+ if (of_dma_is_coherent(eth->dev->of_node)) {
mediatek: rewrite flow offload code The code is now much cleaner and works better than the old code. Preparation for submitting it upstream (though with a different API) Also add back MT7621 support and fix flow table coherence issues on MT7622 Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-10-08 11:44:33 +00:00
+ u32 mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
+ ETHSYS_DMA_AG_MAP_PPE;
mediatek: enable coherent DMA for ethernet and PCI Improves performance by eliminating the need for extra cache flushes Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-09-04 17:41:46 +00:00
+
+ regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, mask, mask);
+ }
+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
ret = device_reset(eth->dev);
if (ret) {
kernel: improve skb hash on the mtk ethernet driver The PPE only provides a 14 bit hash, however many uses of the skb hash expect the hash to use the full 32 bit range. Use jhash to extend the hash to the full size Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-12-18 16:10:04 +00:00
@@ -3083,6 +3091,16 @@ static int mtk_probe(struct platform_dev
mediatek: enable coherent DMA for ethernet and PCI Improves performance by eliminating the need for extra cache flushes Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-09-04 17:41:46 +00:00
}
}
+ if (of_dma_is_coherent(pdev->dev.of_node)) {
+ struct regmap *cci;
+
+ cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "mediatek,cci-control");
+ /* enable CPU/bus coherency */
+ if (!IS_ERR(cci))
+ regmap_write(cci, 0, 3);
+ }
+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
GFP_KERNEL);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
mediatek: rewrite flow offload code The code is now much cleaner and works better than the old code. Preparation for submitting it upstream (though with a different API) Also add back MT7621 support and fix flow table coherence issues on MT7622 Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-10-08 11:44:33 +00:00
@@ -435,6 +435,12 @@
mediatek: enable coherent DMA for ethernet and PCI Improves performance by eliminating the need for extra cache flushes Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-09-04 17:41:46 +00:00
#define RSTCTRL_FE BIT(6)
#define RSTCTRL_PPE BIT(31)
+/* ethernet dma channel agent map */
+#define ETHSYS_DMA_AG_MAP 0x408
+#define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
+#define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
mediatek: rewrite flow offload code The code is now much cleaner and works better than the old code. Preparation for submitting it upstream (though with a different API) Also add back MT7621 support and fix flow table coherence issues on MT7622 Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-10-08 11:44:33 +00:00
+#define ETHSYS_DMA_AG_MAP_PPE BIT(2)
mediatek: enable coherent DMA for ethernet and PCI Improves performance by eliminating the need for extra cache flushes Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-09-04 17:41:46 +00:00
+
/* SGMII subsystem config registers */
/* Register to auto-negotiation restart */
#define SGMSYS_PCS_CONTROL_1 0x0
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